HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 198

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 Refresh Controller
DRAM Interface
To set up area 3 for connection to 16-bit-wide DRAM, initialize RTCOR, RTMCSR, and
RFSHCR in that order, clearing bit PSRAME to 0 and setting bit DRAME to 1. Set bit P8
1 in the port 8 data direction register (P8DDR) to enable CS
16-bit-access area.
Pseudo-Static RAM Interface
To set up area 3 for connection to pseudo-static RAM, initialize RTCOR, RTMCSR, and
RFSHCR in that order, setting bit PSRAME to 1 and clearing bit DRAME to 0. Set bit P8
1 in P8DDR to enable CS
Interval Timer
When PSRAME = 0 and DRAME = 0, the refresh controller operates as an interval timer. After
setting RTCOR, select an input clock in RTMCSR and set the CMIE bit to 1. CMI interrupts will
be requested at compare match intervals determined by RTCOR and bits CKS2 to CKS0 in
RTMCSR.
When setting RTCOR, RTMCSR, and RFSHCR, make sure that PSRAME = 0 and DRAME = 0.
Writing is disabled when either of these bits is set to 1.
Rev. 3.00 Sep 27, 2006 page 170 of 872
REJ09B0325-0300
3
output.
3
output. In ABWCR, make area 3 a
1
1
DDR to
DDR to