HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 163

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.3.2
For each of areas 7 to 0, the H8/3048B Group can output a chip select signal (CS
low to indicate when the area is selected. Figure 6.3 shows the output timing of a CS
to 7).
Output of CS
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS
pins CS
bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins CS
CS
be set to 1. For details see section 9, I/O Ports.
Output of CS
register (CSCR). A reset leaves pins CS
to CS
When the on-chip ROM, on-chip RAM, and internal I/O registers are accessed, CS
remain high. The CS
select signals for SRAM and other devices.
0
in the input state. To output chip select signals CS
4
, the corresponding CSCR bits must be set to 1. For details see section 9, I/O Ports.
3
to CS
Chip Select Signals
CS
CS
CS
CS
CS
CS
3
7
1
to CS
to CS
in the input state. To output chip select signals CS
Address
bus
CS
CS
CS
CS
CS
CS
CS
n
n
0
4
: Output of CS
: Output of CS
signals are decoded from the address signals. They can be used as chip
Figure 6.3 CS
3
7
to CS
to CS
CS
CS
CS
7
to CS
n
0
4
Output Timing (n = 7 to 0)
is enabled or disabled in the data direction register
is enabled or disabled in the chip select control
External address in area n
4
in the input state. To output chip select signals CS
3
to CS
Rev. 3.00 Sep 27, 2006 page 135 of 872
0
, the corresponding DDR bits must
3
to CS
1
Section 6 Bus Controller
, the corresponding DDR
0
in the output state and
REJ09B0325-0300
7
to CS
7
and CS
n
signal (n = 0
0
) that goes
0
3
to
7