HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 306

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 9 I/O Ports
Mode 7 (Single-Chip Mode): Port 5 functions as an input/output port. A pin in port 5 becomes an
output port if the corresponding P5DDR bit is set to 1, and an input port if this bit is cleared to 0.
In modes 1 to 4, P5DDR always returns 1 when read. No value can be written to.
In modes 5 to 7, P5DDR is a write-only register. Its value cannot be read. All bits return 1 when
read.
P5DDR is initialized to H'FF in modes 1 to 4 and H'F0 in modes 5 to 7 by a reset and in hardware
standby mode. In software standby mode it retains its previous setting, so if a P5DDR bit is set to
1 while port 5 acts as an I/O port, the corresponding pin maintains its output state in software
standby mode.
Port 5 Data Register (P5DR)
P5DR is an 8-bit readable/writable register that stores output data for pins P5
acts as an output port, the value of this register is output. When a bit in P5DDR is set to 1, if port 5
is read the value of the corresponding P5DR bit is returned. When a bit in P5DDR is cleared to 0,
if port 5 is read the corresponding pin level is read.
Bits 7 to 4 are reserved. They cannot be modified and are always read as 1.
P5DR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev. 3.00 Sep 27, 2006 page 278 of 872
REJ09B0325-0300
Bit
Initial value
Read/Write
7
1
Reserved bits
6
1
5
1
4
1
R/W
P5
3
0
3
Port 5 data 3 to 0
These bits store data
for port 5 pins
R/W
P5
2
0
2
3
to P5
R/W
P5
1
0
1
0
. While port 5
R/W
P5
0
0
0