HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 668

MCU 5V 0K PB-FREE 112-QFP

HD6413003TF16V

Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413003TF16V

Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6413003TF16V
Manufacturer:
ITT
Quantity:
12 000
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS
Quantity:
36
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
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SSR—Serial Status Register
Transmit data register empty
Note: Only 0 can be written, to clear the flag.
0
1
Receive data register full
Bit
Initial value
Read/Write
0
1
[Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
The DMAC writes data in TDR.
[Setting conditions]
Reset or transition to standby mode.
TE is 0 in SCR
Data is transferred from TDR to TSR, enabling new
data to be written in TDR.
*
[Clearing conditions]
Reset or transition to standby mode.
Read RDRF when RDRF = 1, then write 0 in
RDRF.
The DMAC reads data from RDR.
[Setting condition]
Serial data is received normally and transferred
from RSR to RDR
Framing error
0
1
[Clearing conditions]
Reset or transition to standby mode.
Read FER when FER = 1, then write 0
in FER.
[Setting condition]
Framing error (stop bit is 0)
Transmit end
0
1
R/(W)
TDRE
[Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
The DMAC writes data in TDR.
[Setting conditions]
Reset or transition to standby mode.
TE is cleared to 0 in SCR.
TDRE is 1 when last bit of serial character is transmitted.
7
1
*
R/(W)
RDRF
6
0
*
Multiprocessor bit
0
1
ORER
R/(W)
Multiprocessor bit value in
receive data is 0
Multiprocessor bit value in
receive data is 1
5
0
*
648
R/(W)
FER
4
0
Parity error
Overrun error
0
1
0
1
*
[Clearing conditions]
Reset or transition to standby mode.
Read PER when PER = 1, then write 0 in
PER.
[Setting condition]
Parity error: (parity of receive data does not
match parity setting of O/
[Clearing conditions]
Reset or transition to standby mode.
Read ORER when ORER = 1, then write 0 in
ORER.
[Setting condition]
Overrun error (reception of next serial data
ends when RDRF = 1)
R/(W)
PER
3
0
*
H'B4
Multiprocessor bit transfer
TEND
0
1
R
2
1
Multiprocessor bit value in
transmit data is 0
Multiprocessor bit value in
transmit data is 1
E
MPB
in SMR)
R
1
0
MPBT
R/W
SCI0
0
0

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