HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet
HD6413003TF16V
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HD6413003TF16V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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H8/3003 Hardware Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. ...
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The H8/3003 is a high-performance microcontroller that integrates system supporting functions together with an H8/300H CPU core. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It ...
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Section 1 Overview 1.1 Overview ........................................................................................................................ 1.2 Block Diagram................................................................................................................ 1.3 Pin Description ............................................................................................................... 1.3.1 Pin Arrangement............................................................................................. 1.3.2 Pin Functions .................................................................................................. 1.4 Pin Functions .................................................................................................................. 11 Section 2 CPU ............................................................................................................... 17 2.1 Overview ........................................................................................................................ 17 2.1.1 Features........................................................................................................... 17 2.1.2 Differences from ...
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Basic Operational Timing............................................................................................... 53 2.9.1 Overview......................................................................................................... 53 2.9.2 On-Chip Memory Access Timing................................................................... 53 2.9.3 On-Chip Supporting Module Access Timing ................................................. 55 2.9.4 Access to External Address Space.................................................................. 56 Section 3 MCU Operating Modes 3.1 Overview ........................................................................................................................ 57 3.1.1 Operating ...
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Register Descriptions...................................................................................................... 76 5.2.1 System Control Register (SYSCR)................................................................. 76 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ....................................... 77 5.2.3 IRQ Status Register (ISR) .............................................................................. 84 5.2.4 IRQ Enable Register (IER) ............................................................................. 85 5.2.5 IRQ Sense Control Register ...
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Register Write Timing .................................................................................... 132 BREQ Input Timing........................................................................................ 133 6.4.3 Section 7 Refresh Controller 7.1 Overview ........................................................................................................................ 135 7.1.1 Features........................................................................................................... 135 7.1.2 Block Diagram................................................................................................ 136 7.1.3 Input/Output Pins............................................................................................ 137 7.1.4 Register Configuration.................................................................................... 137 7.2 Register Descriptions...................................................................................................... 138 7.2.1 Refresh ...
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I/O Mode......................................................................................................... 198 8.4.3 Idle Mode........................................................................................................ 200 8.4.4 Repeat Mode................................................................................................... 203 8.4.5 Normal Mode.................................................................................................. 206 8.4.6 Block Transfer Mode ...................................................................................... 209 8.4.7 DMAC Activation........................................................................................... 214 8.4.8 DMAC Bus Cycle ........................................................................................... 216 8.4.9 Multiple-Channel Operation........................................................................... 222 8.4.10 External Bus Requests, ...
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Port 7 ........................................................................................................................ 252 9.5.1 Overview......................................................................................................... 252 9.5.2 Register Description ....................................................................................... 253 9.6 Port 8 ........................................................................................................................ 254 9.6.1 Overview......................................................................................................... 254 9.6.2 Register Descriptions...................................................................................... 254 9.6.3 Pin Functions .................................................................................................. 256 9.7 Port 9 ........................................................................................................................ 257 9.7.1 Overview......................................................................................................... 257 9.7.2 Register ...
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Timer I/O Control Register (TIOR)................................................................ 310 10.2.12 Timer Status Register (TSR)........................................................................... 312 10.2.13 Timer Interrupt Enable Register (TIER)......................................................... 315 10.3 CPU Interface ................................................................................................................. 317 10.3.1 16-Bit Accessible Registers ............................................................................ 317 10.3.2 8-Bit Accessible Registers .............................................................................. 319 10.4 Operation ........................................................................................................................ ...
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Output Timing................................................................................................. 399 11.3.3 Normal TPC Output........................................................................................ 400 11.3.4 Non-Overlapping TPC Output........................................................................ 402 11.3.5 TPC Output Triggering by Input Capture....................................................... 404 11.4 Usage Notes .................................................................................................................... 405 11.4.1 Operation of TPC Output Pins........................................................................ 405 11.4.2 Note on Non-Overlapping Output .................................................................. ...
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Bit Rate Register (BRR) ................................................................................. 441 13.3 Operation ........................................................................................................................ 450 13.3.1 Overview......................................................................................................... 450 13.3.2 Operation in Asynchronous Mode.................................................................. 452 13.3.3 Multiprocessor Communication ..................................................................... 461 13.3.4 Synchronous Operation .................................................................................. 468 13.4 SCI Interrupts.................................................................................................................. 477 13.5 Usage Notes .................................................................................................................... 478 Section ...
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System Clock Divider (Clock-Halving Version) ............................................................ 510 16.4 Duty Adjustment Circuit (1:1 Version)........................................................................... 510 16.5 Prescalers ........................................................................................................................ 510 Section 17 Power-Down State 17.1 Overview ........................................................................................................................ 511 17.2 Register Configuration.................................................................................................... 512 17.2.1 System Control Register (SYSCR)................................................................. 512 17.3 Sleep Mode ...
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Appendix A Instruction Set A.1 Instruction List................................................................................................................ 553 A.2 Operation Code Map....................................................................................................... 568 A.3 Number of States Required for Execution...................................................................... 571 Appendix B Register Field B.1 Register Addresses and Bit Names................................................................................. 580 B.2 Register Descriptions...................................................................................................... 589 Appendix C I/O Port ...
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Major Revisions and Additions in This Version Page Item P96 Figure 5-7 Interrupt Sequence (Mode 2, Two-State Access, Stack in External Memory) P97 Table 5-5 Interrupt Response Time P125 Figure 6-15 Programmable Wait Mode P132 Figure 6-20 ASTCR Write Timing ...
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Page Item P514 17.3.2 Exit from Sleep Mode Exit by Interrupt P529 to Table 18-4 Electrical Characteristics P536 to 18-8 P520 to Table 18-2 DC Characteristics P526 P529 to Table 18-4 Bus Timing P531 P532 Table 18-5 Refresh Controller Bus ...
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Overview The H8/3003 is a microcontroller (MCU) that integrates system supporting functions together with an H8/300H CPU core having an original Hitachi architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, ...
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Table 1-1 Features (cont) Feature Description Memory RAM: 512 bytes Interrupt • Nine external interrupt pins: NMI, IRQ controller • 34 internal interrupts • Three selectable interrupt priority levels Bus controller • Address space can be partitioned into eight areas, ...
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Table 1-1 Features (cont) Feature Description 16-bit integrated • Five 16-bit timer channels, capable of processing pulse outputs or 10 timer unit (ITU) pulse inputs • 16-bit timer counter (channels • Two multiplexed output ...
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Table 1-1 Features (cont) Feature Description Operating modes Four MCU operating modes Mode Mode 1 Mode 2 Mode 3 Mode 4 Power-down • Sleep mode state • Software standby mode • Hardware standby mode Other features • On-chip clock oscillator ...
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Block Diagram Figure 1-1 shows an internal block diagram EXTAL XTAL ø STBY RES RESO NMI AS RD HWR LWR P6 /BACK 2 P6 /BREQ 1 P6 /WAIT ...
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Pin Description 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the H8/3003’s QFP-112 package. 112 111 110 109 108 107 106 105 104 103 102 101 100 ...
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Pin Functions Pin Assignments in Each Mode: Table 1-2 lists the QFP-112 pin assignments in each mode. Table 1-2 QFP-112 Pin Assignments in Each Mode Pin No. Mode /TP /TIOCA ...
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Table 1-2 QFP-112 Pin Assignments in Each Mode (cont) Pin No. Mode 1 Mode ...
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Table 1-2 QFP-112 Pin Assignments in Each Mode (cont) Pin No. Mode 1 Mode ...
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Table 1-2 QFP-112 Pin Assignments in Each Mode (cont) Pin Mode 1 Mode 2 No ref ...
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Pin Functions Table 1-3 summarizes the pin functions. Table 1-3 Pin Functions Type Symbol Power Clock XTAL EXTAL ø Operating mode control Pin No. QFP-112 I/O Name and Function 1, 44, ...
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Table 1-3 Pin Functions (cont) Type Symbol System control RES RESO STBY BREQ BACK Interrupts NMI IRQ to 7 IRQ 0 Address bus Data bus Bus control ...
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Table 1-3 Pin Functions (cont) Type Symbol Refresh RFSH controller HWR LWR DMA DREQ to 3 controller DREQ 0 (DMAC) TEND to 3 TEND 0 16-bit TCLKD to integrated TCLKA time unit TIOCA to 4 (ITU) TIOCA ...
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Table 1-3 Pin Functions (cont) Type Symbol Programmable timing pattern TP 0 controller (TPC) Serial com- TxD , 1 munication TxD 0 interface (SCI) RxD , 1 RxD 0 SCK , 0 SCK 1 A ...
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Table 1-3 Pin Functions (cont) Type Symbol I/O ports Pin No. QFP-112 I/O Name and Function Input/ ...
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16 ...
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Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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High-speed operation — All frequently-used instructions execute in two to four states — Maximum clock frequency: — 8/16/32-bit register-register add/subtract: 125 ns — 8 8-bit register-register multiply: — 16 ÷ 8-bit register-register divide: — 16 16-bit register-register multiply: — ...
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CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports Mbytes. See figure 2-1. The H8/3003 uses only advanced mode. CPU operating ...
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Address Space The maximum address space of the H8/300H CPU is 16 Mbytes. The H8/3003 has two operating modes (MCU modes), one providing a 1-Mbyte address space, the other supporting the full 16 Mbytes. Figure 2-2 shows the H8/3003’s ...
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Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2-3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 Control ...
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General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, ...
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General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-5 shows the stack. SP (ER7) 2.4.3 Control Registers The control registers are ...
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Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, ...
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Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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General Data Type Register Word data Rn MSB Word data En MSB Longword data ERn MSB Legend ERn: General register En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit ...
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Data Type 1-bit data Byte data Word data Longword data When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. Address 7 Address 7 6 Address MSB ...
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Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified in table 2-1. Table 2-1 Instruction Classification Function Instruction Data transfer MOV, PUSH Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, ...
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Instructions and Addressing Modes Table 2-2 indicates the instructions available in the H8/300H CPU. Table 2-2 Instructions and Addressing Modes Function Instruction #xx Rn Data MOV BWL BWL BWL transfer POP, PUSH — — MOVFPE, — — MOVTPE Arithmetic ...
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Tables of Instructions Classified by Function Tables 2-3 to 2-10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation Rd General register (destination)* Rs General register (source)* Rn General ...
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Table 2-3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) Cannot be used in the ...
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Table 2-4 Arithmetic Operation Instructions Instruction Size* Function ADD, B/W/L Rd ± Rs SUB Performs addition or subtraction on data in two general registers immediate data and data in a general register. (Immediate byte data cannot be subtracted ...
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Table 2-4 Arithmetic Operation Instructions (cont) Instruction Size* Function DIVXU B/W Rd ÷ Rs Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits 16-bit quotient and 16-bit remainder. DIVXS B/W Rd ÷ Rs Performs ...
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Table 2-5 Logic Operation Instructions Instruction Size* Function AND B/W Performs a logical AND operation on a general register and another general register or immediate data. OR B/W Performs a logical OR operation on a general ...
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Table 2-7 Bit Manipulation Instructions Instruction Size* Function BSET B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 ...
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Table 2-7 Bit Manipulation Instructions (cont) Instruction Size* Function BOR B C (<bit-No.> of <EAd>) ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIOR B ...
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Table 2-8 Branching Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS Bcc (BHS) BCS (BLO) BNE BEQ BVC ...
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Table 2-9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling RTE — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state LDC B/W (EAs) Moves the source operand contents to the ...
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Table 2-10 Block Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B — repeat @ER5+ until else next ≠ 0 then EEPMOV.W — repeat @ER5+ until else next; Transfers a data block according to parameters set ...
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Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates ...
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Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used ...
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Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers and ...
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Table 2-12 Absolute Address Access Ranges Absolute Address 1-Mbyte Modes 8 bits (@aa:8) H'FFF00 to H'FFFFF (1048320 to 1048575) 16 bits (@aa:16) H'00000 to H'07FFF, H'F8000 to H'FFFFF (0 to 32767, 1015808 to 1048575) 24 bits (@aa:24) H'00000 to H'FFFFF ...
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Specified by @aa:8 Figure 2-10 Memory-Indirect Branch Address Specification When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. ...
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Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2-11 ...
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Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, ...
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Reset Exception Interrupt sources Trap instruction Figure 2-12 Classification of Exception Sources End of bus release Bus request Bus-released state End of exception handling Exception-handling state RES = 1 *1 Reset state Notes: 1. From any state except hardware standby ...
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Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is RES signal goes low. Reset exception handling starts after that, when RES entered when the changes from low to high. When reset exception ...
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Bus-Released State In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU are the DMA controller, the refresh controller, and an ...
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Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the system clock to the next rise is referred “state.” A memory cycle or bus ...
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Address bus AS RD HWR LWR , , , Figure 2-16 Pin States during On-Chip Memory Access Address High High impedance 54 ...
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On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus bits wide, depending on the register being accessed. Figure 2-17 shows the on-chip supporting module access timing. Figure ...
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Address bus AS RD HWR LWR , , , Figure 2-18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3003 has four operating modes (modes that are selected by the mode pins ( indicated in table 3-1. The input at these ...
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Register Configuration The H8/3003 has a mode control register (MDCR) that indicates the inputs at the mode pins ( and a system control register (SYSCR). Table 3-2 summarizes these registers Table 3-2 Registers Address* ...
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Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3003. Bit 7 — Initial value 1 Read/Write — Reserved bits Note: Determined by pins Bits ...
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System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3003. Bit 7 SSBY STS2 Initial value 0 Read/Write R/W Software standby Enables transition to software standby mode Bit 7—Software Standby (SSBY): Enables transition ...
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Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. ...
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Operating Mode Descriptions 3.4.1 Mode 1 Address pins are enabled, permitting access to a maximum 1-Mbyte address space. The 19 0 initial bus mode after a reset is 8 bits, with 8-bit access to all areas. ...
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Pin Functions in Each Operating Mode The pin functions of ports 4 and 5 vary depending on the operating mode. Table 3-3 indicates their functions in each operating mode. Table 3-3 Pin Functions in Each Mode Port Mode 1 ...
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Modes 1 and 2 (1-Mbyte modes) H'00000 Vector table H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'F8000 H'FFD0F H'FFD10 On-chip RAM * H'FFF00 H'FFF0F H'FFF10 External address space H'FFF1B ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or ...
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Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vectors are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. • Reset Exception • Interrupts sources • Trap ...
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Reset 4.2.1 Overview A reset is the highest-priority exception. When the H8/3003 enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception handling begins when the ...
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Figure 4-2 Reset Sequence (Modes 1 and 3) 68 ...
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RES Address bus RD HWR LWR , High (1), (3) Address of reset vector: (1) = H'00000, (3) = H'00002 (2), (4) Start address (contents of reset vector) (5) Start address (6) First instruction ...
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Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ 34 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set the system control register (SYSCR), the exception handling sequence sets the I bit CCR. ...
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Notes on Stack Usage When accessing word data or longword data, the H8/3003 regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in ...
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Block Diagram Figure 5-1 shows a block diagram of the interrupt controller. ISCR NMI input IRQ input OVF TME . . . . . . . . . . ADI ADIE Interrupt controller Legend I: Interrupt mask bit IER: ...
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Pin Configuration Table 5-1 lists the interrupt pins. Table 5-1 Interrupt Pins Name Nonmaskable interrupt External interrupt request IRQ 5.1.4 Register Configuration Table 5-2 lists the registers of the interrupt controller. Table 5-2 Interrupt Controller Registers ...
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Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only ...
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Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 UE Description 0 UI bit in CCR is used as interrupt mask bit 1 UI ...
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Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRA7 Initial value 0 Read/Write R/W Priority level A6 Selects the priority level of IRQ interrupt requests Priority level ...
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Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ Bit 7 IPRA7 Description 0 IRQ interrupt requests have priority level 0 (low priority IRQ interrupt requests have priority level 1 (high priority) 0 Bit 6—Priority Level ...
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Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT and refresh controller interrupt requests. Bit 3 IPRA3 Description 0 WDT and refresh controller interrupt requests have priority level 0 (low priority) 1 WDT and refresh controller interrupt requests ...
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Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRB7 IPRB6 Initial value 0 Read/Write R/W Priority level B7 Selects the priority level of ITU channel 3 interrupt ...
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Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests. Bit 7 IPRB7 Description 0 ITU channel 3 interrupt requests have priority level 0 (low priority) 1 ITU channel 3 interrupt requests have priority level ...
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Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests. Bit 3 IPRB3 Description 0 SCI0 interrupt requests have priority level 0 (low priority) 1 SCI0 interrupt requests have priority level 1 (high priority) Bit ...
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IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ requests. Bit 7 IRQ7F Initial value 0 Read/Write R/(W) * Note: * Only 0 can be written, to clear flags. ISR is initialized ...
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IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ Bit 7 IRQ7E IRQ6E Initial value 0 Read/Write R/W IER is initialized to H' reset and in hardware standby mode. Bits 7 ...
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IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ to IRQ . 7 0 Bit 7 IRQ7SC IRQ6SC Initial value 0 Read/Write R/W ISCR ...
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Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ 5.3.1 External Interrupts There are nine external interrupts: NMI, and IRQ can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt and is always accepted, ...
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Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF). ø IRQn input pin IRQnF Figure 5-3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector numbers 12 to 19. These interrupts are detected regardless ...
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Table 5-3 Interrupt Sources, Vector Addresses, and Priority Interrupt Source NMI IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 WOVI (interval timer) CMI (compare match) Reserved IMIA0 (compare match/input capture A0) IMIB0 ...
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Table 5-3 Interrupt Sources, Vector Addresses, and Priority (cont) Interrupt Source IMIA3 (compare match/input capture A3) IMIB3 (compare match/input capture B3) OVI3 (overflow 3) Reserved IMIA4 (compare match/input capture A4) IMIB4 (compare match/input capture B4) OVI4 (overflow 4) Reserved DEND0A ...
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Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3003 handles interrupts differently depending on the setting of the UE bit. When interrupts are controlled by the I bit. When interrupts are controlled by the ...
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Program execution state Interrupt requested? Yes Priority level 1? Yes No IRQ 0 Yes No IRQ 1 Yes ADI Yes Save PC and CCR Read vector address Branch to interrupt Figure 5-4 Process Up to Interrupt Acceptance when UE = ...
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If an interrupt condition occurs and the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. • When the interrupt controller receives one or more interrupt requests, it selects the highest- ...
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Figure 5-5 shows the transitions among the above states. a. All interrupts are unmasked I 0 Figure 5-5 Interrupt Masking State Transitions (Example) Figure 5 flowchart showing how interrupts are accepted when • ...
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Program execution state Interrupt requested? Yes Priority level 1? Yes No IRQ 0 Yes No IRQ 1 Yes ADI Yes Yes Yes Save PC and CCR Read vector address Branch to interrupt Figure 5-6 Process Up to ...
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Interrupt Sequence Figure 5-7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5-7 Interrupt Sequence (Mode 2, Two-State Access, ...
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Interrupt Response Time Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5-5 Interrupt Response Time No. Item 1 Interrupt priority decision ...
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Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed interrupt ...
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Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting ...
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Section 6 Bus Controller 6.1 Overview The H8/3003 has an on-chip bus controller that divides the address space into eight areas and can assign different bus specifications to each. This enables different types of memory to be connected easily. A ...
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Block Diagram Figure 6-1 shows a block diagram of the bus controller. Internal address bus Area decoder WAIT Internal signals CPU bus request signal DMAC bus request signal Refresh controller bus request signal CPU bus acknowledge signal DMAC bus ...
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Input/Output Pins Table 6-1 summarizes the bus controller’s input/output pins. Table 6-1 Bus Controller Pins Name Abbreviation Chip select Address strobe RD Read HWR High write LWR Low write WAIT Wait ...
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Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area. Bit 7 ABW7 Mode Initial value Mode Read/Write R/W When ...
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Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. Bit 7 AST7 Initial value 1 Read/Write R/W ASTCR is initialized to H' ...
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Wait Control Register (WCR) WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. Bit 7 — Initial value 1 Read/Write — WCR is initialized to ...
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Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted in access to external three-state-access areas. Bit 1 Bit 0 WC1 WC0 Description wait states inserted by wait-state controller ...
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Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables or disables release of the bus to an external device. Bit 7 — Initial value 1 Read/Write — BRCR is initialized to H' reset ...
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Operation 6.3.1 Area Division The external address space is divided into areas Each area has a size of 128 kbytes in the 1-Mbyte modes Mbytes in the 16-Mbyte modes. Figure 6-2 shows a general ...
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Chip select signals ( can be selected in ABWCR, ASTCR, WCER, and WCR as shown in table 6-3. Table 6-3 Bus Specifications ABWCR ASTCR WCER ABWn ASTn WCEn 0 0 — — ...
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Chip Select Signals For each of areas the H8/3003 can output a chip select signal (CS indicate when the area is selected. Figure 6-3 shows the output timing of a CSn signal. Output of the CS ...
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Data Bus The H8/3003 allows either 8-bit access or 16-bit access to be designated for each of areas 8-bit-access area uses the upper data bus (D data bus ( and lower data ...
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Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6-4 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper address bus (D pin is always high. Wait states can be inserted. ø Address bus CS ...
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Two-State-Access Areas: Figure 6-5 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper address bus (D pin is always high. Wait states cannot be inserted. ø Address bus Read D ...
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Three-State-Access Areas: Figures 6-6 to 6-8 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper address bus (D even addresses and the lower address bus (D can be inserted. ø Address ...
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Address bus Read access HWR LWR Write access Figure 6-7 Bus Control Signal Timing for ...
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Address bus Read access HWR LWR Write access Figure 6-8 Bus Control Signal Timing for ...
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Two-State-Access Areas: Figures 6-9 to 6-11 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper address bus (D even addresses and the lower address bus (D cannot be inserted. ø Address ...
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Address bus Read access HWR LWR Write access Note Figure ...
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Address bus Read access HWR LWR Write access Note Figure ...
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Wait Modes Four wait modes can be selected for each area as shown in table 6-5. Table 6-5 Wait Mode Selection ASTCR WCER ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control 0 — — — ...
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Pin Wait Mode 0: The wait state controller is disabled. Wait states can only be inserted by WAIT pin control. During access to an external three-state-access area, if the WAIT pin is low at the fall of the system clock ...
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Pin Wait Mode 1: In all accesses to external three-state-access areas, the number of wait states ) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system (T W clock ...
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Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (T WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (ø) in the ...
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Programmable Wait Mode: The number of wait states (T inserted in all accesses to external three-state-access areas. Figure 6-15 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). ø Address bus AS RD Read ...
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Example of Wait State Control Settings: A reset initializes ASTCR and WCER to H'FF and WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can select other wait modes for individual areas by modifying ...
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Interconnections with Memory (Example) For each area, the bus controller can select two- or three-state access and 16-bit data bus width. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the ...
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H8/3003 WAIT RD HWR LWR Figure 6-18 Interconnections between H8/3003 and Memory (Example ...
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Bus Arbiter Operation The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are four bus masters: the CPU, DMA controller (DMAC), refresh controller, and an external bus master. When a bus master has ...
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DMAC: When the DMAC receives an activation request, it requests the bus right from the bus arbiter. If DMAC is a bus master and the refresh controller or an external bus master requests the bus, the bus arbiter transfers the ...
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Figure 6-19 shows the timing when the bus right is requested by an external bus master during a read cycle in a two-state-access area. There is a minimum interval of two states from when the BREQ signal goes low until ...
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Usage Notes 6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM A different bus control signal timing applies when dynamic RAM or pseudo-static RAM is connected to area 3. For details see section 7, Refresh Controller. 6.4.2 Register Write Timing ...
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DDR Write Timing: Data written to a data direction register (DDR) to change output to generic input, or vice versa, takes effect starting from the T n cycle. Figure 6-21 shows the timing when the CS output. ...
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134 ...
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Section 7 Refresh Controller 7.1 Overview The H8/3003 has an on-chip refresh controller that enables direct connection of 16-bit-wide DRAM or pseudo-static RAM (PSRAM). DRAM or pseudo-static RAM can be directly connected to area 3 of the external address space. ...
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Features as an Interval Timer • Refresh timer counter (RTCNT) can be used as an 8-bit up-counter • Selection of seven counter clock sources: ø/2, ø/8, ø/32, ø/128, ø/512, ø/2048, ø/4096 • Interrupts can be generated by compare match between ...
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Input/Output Pins Table 7-1 summarizes the refresh controller’s input/output pins. Table 7-1 Refresh Controller Pins Signal Pin Name RFSH Refresh HWR Upper write/upper column address strobe LWR Lower write/lower column address strobe RD Column address strobe/ write enable CS ...
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Register Descriptions 7.2.1 Refresh Control Register (RFSHCR) RFSHCR is an 8-bit readable/writable register that selects the operating mode of the refresh controller. Bit 7 SRFMD PSRAME Initial value 0 Read/Write R/W PSRAM enable and DRAM enable These bits enable ...
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Bit 7—Self-Refresh Mode (SRFMD): Specifies DRAM or pseudo-static RAM self-refresh during software standby mode. When PSRAME = 1 and DRAME = 0, after the SRFMD bit is set to 1, pseudo-static RAM can be self-refreshed when the H8/3003 enters software ...
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Bit 4—Strobe Mode Select valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled when the PSRAME or DRAME bit is set to 1. Bit 4 CAS/WE Description 0 2WE mode 1 2CAS mode Bit 3—Address Multiplex ...
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Refresh Timer Control/Status Register (RTMCSR) RTMCSR is an 8-bit readable/writable register that selects the clock source for RTCNT. It also enables or disables interrupt requests when the refresh controller is used as an interval timer. Bit 7 CMF Initial ...
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Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt requested when the CMF flag is set RTMCSR. The CMIE bit is always cleared to 0 when PSRAME = 1 or DRAME = 1. Bit ...
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Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. Bit 7 Initial value 0 Read/Write R/W RTCNT is an up-counter that is incremented by an internal clock selected by bits CKS2 to CKS0 in RTMCSR. When RTCNT matches ...
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Operation 7.3.1 Area Division One of three functions can be selected for the H8/3003 refresh controller: interfacing to DRAM connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval timing. Table 7-3 summarizes the register ...
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Interval Timer: When PSRAME = 0 and DRAME = 0, the refresh controller operates as an interval timer. After setting RTCOR, select an input clock in RTMCSR and set the CMIE bit to 1. CMI interrupts will be requested at ...
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Table 7-4 Area 3 Settings, DRAM Access Cycles, and Refresh Cycles Area 3 Settings Read/Write Cycle by CPU or DMAC 2-state-access area • 3 states (AST3 = 0) • Wait states cannot be inserted 3-state-access area • 3 states (AST3 ...
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Address Multiplexing: Address multiplexing depends on the setting of the M9/M8 bit in RFSHCR, as described in table 7-5. Figure 7-4 shows the address output timing. Address output is multiplexed only in area 3. Table 7-5 Address Multiplexing Address Pins ...
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Modes: The CAS/WE bit in RFSHCR can select two control modes for 16-bit- wide DRAM: one using UCAS and LCAS; the other using UW and LW. These DRAM pins correspond to H8/3003 pins as shown in table ...
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Read cycle ø Address Row Column bus CS 3 RAS ( ) HWR UCAS ( ) LWR LCAS ( ) RFSH AS Note: 16-bit access * Figure 7-5 DRAM Control Signal Output Timing (2) (2CAS Mode) ...
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Self-Refresh Mode: Some DRAM devices have a self-refresh function. After the SRFMD bit is set RFSHCR, when a transition to software standby mode occurs, the CAS and RAS outputs go low in that order so that the ...
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Address bus CS (RAS (CAS) HWR (UW) High LWR (LW) High RFSH ø Address CS (RAS) 3 HWR (UCAS) LWR (LCAS) RD (WE) RFSH Figure 7-6 Signal Output Timing in Self-Refresh Mode (PSRAME = 0, DRAME = ...
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Operation in Power-Down State: The refresh controller operates in sleep mode. It does not operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR, RTMCSR bits and RTCOR retain their settings prior to ...
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Set area 3 for 16-bit access Set P8 DDR to 1 for 1 Set bits CKS2 to CKS0 in RTMCSR Write H'23 in RFSHCR Wait for DRAM to be initialized DRAM can be accessed Figure 7-8 Setup Procedure for 2WE ...
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Example 2: Connection to 2WE 4-Mbit DRAM (16-Mbyte Mode): Figure 7-9 shows typical interconnections to a single 2WE 4-Mbit DRAM, and the corresponding address map. Figure 7-10 shows a setup procedure to be followed by a program for this example. ...
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Set P8 DDR to 1 for Set bits CKS2 to CKS0 in RTMCSR Figure 7-10 Setup Procedure for 2WE 4-Mbit DRAM with 10-Bit Row Address and 8-Bit Column Address (16-Mbyte Mode) Set area 3 for 16-bit access CS output 1 ...
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Example 3: Connection to 2CAS 4-Mbit DRAM (16-Mbyte Mode): Figure 7-11 shows typical interconnections to a single 2CAS 4-Mbit DRAM, and the corresponding address map. Figure 7-12 shows a setup procedure to be followed by a program for this example. ...
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Set P8 DDR to 1 for Set bits CKS2 to CKS0 in RTMCSR Figure 7-12 Setup Procedure for 2CAS 4-Mbit DRAM with 9-Bit Row Address and 9-Bit Column Address (16-Mbyte Mode) Set area 3 for 16-bit access CS output 1 ...
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Example 4: Connection to Two 4-Mbit DRAM Chips (16-Mbyte Mode): Figure 7-13 shows an example of interconnections to two 2CAS 4-Mbit DRAM chips, and the corresponding address map four DRAM chips can be connected to area 3 by ...
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Set P8 DDR to 1 for CS output Set bits CKS2 to CKS0 in RTMCSR Wait for DRAM to be initialized Figure 7-14 Setup Procedure for Multiple 2CAS 4-Mbit DRAM Chips with 9-Bit Row Address and 9-Bit Column Address (16-Mbyte ...
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Pseudo-Static RAM Refresh Control Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is determined DRAM interface, by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR. The numbers of states required ...
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Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is: (High) External bus master > refresh controller > DMA controller > CPU For details see section 6.3.7, Bus Arbiter Operation. Wait State Insertion: When bit AST3 ...
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Address bus High HWR LWR RFSH Figure 7-16 Signal Output Timing in Self-Refresh Mode (PSRAME = 1, DRAME = 0) Operation in Power-Down State: The refresh controller operates in sleep mode. It does not operate in ...
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Example: Pseudo-static RAM may have separate OE and RFSH pins, or these may be combined into a single OE/RFSH pin. Figure 7-17 shows an example of a circuit for generating an OE/RFSH signal. Check the device characteristics carefully, and design ...
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Set P8 DDR to 1 for CS output 1 Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'47 in RFSHCR Wait for PSRAM to be initialized PSRAM can be accessed Figure 7-18 Setup Procedure for Pseudo-Static RAM 164 ...
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Interval Timing To use the refresh controller as an interval timer, clear the PSRAME and DRAME both to 0. After setting RTCOR, select a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to ...
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Contention between RTCNT Write and Counter Clear counter clear signal occurs in the T state of an RTCNT write cycle, clearing of the counter takes priority and the write is not 3 performed. See figure 7-20. ø Address ...
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Contention between RTCNT Write and Increment increment pulse occurs in the RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 7-21. ø Address Internal write signal RTCNT input clock RTCNT Figure ...
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Contention between RTCOR Write and Compare Match compare match occurs in the T state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited. See figure 7-22. ø Address Internal write signal RTCNT ...
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Table 7-9 Internal Clock Switchover and RTCNT Operation CKS2 to CKS0 No. Write Timing *1 1 Low low switchover 2 Low high switchover Notes: 1. Including switchovers from a low clock source to the halted state, and from the halted ...
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Table 7-9 Internal Clock Switchover and RTCNT Operation (cont) CKS2 to CKS0 No. Write Timing 3 High low switchover 4 High high switchover Notes: 1. Including switchover from a high clock source to the halted state. 2. The switchover is ...
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Interrupt Source Compare match interrupts (CMI) can be generated when the refresh controller is used as an interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit of RTMCSR. 7.5 Usage Notes When using the DRAM or ...
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If a bus cycle is prolonged by insertion of wait states, the first refresh request is held the bus-released state. • If contention occurs between a transition to software standby mode and a bus request from an ...
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Section 8 DMA Controller 8.1 Overview The H8/3003 has an on-chip DMA controller (DMAC) that can transfer data eight channels. 8.1.1 Features DMAC features are listed below. • Selection of short address mode or full address mode ...
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Block Diagram Figure 8-1 shows a DMAC block diagram. The DMAC is divided into two groups (group 0 and group 1) of four channels each. Internal IMIA0 interrupts IMIA1 IMIA2 IMIA3 TXI0 RXI0 DREQ0 Control logic DREQ1 TEND0 TEND1 ...
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Functional Overview Table 8-1 gives an overview of the DMAC functions. Table 8-1 DMAC Functional Overview Transfer Mode Short I/O mode address • Transfers one byte or one word mode per request • Increments or decrements the memory address ...
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Input/Output Pins Table 8-2 lists the DMAC pins. Table 8-2 DMAC Pins Group Channel Name 0 0 DMA request 0 Transfer end 0 1 DMA request 1 Transfer end DMA request 2 Transfer end 2 3 ...
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Table 8-3 DMAC Registers Group Channel Address H'FF20 H'FF21 H'FF22 H'FF23 H'FF26 H'FF24 H'FF25 H'FF27 H'FF28 H'FF29 H'FF2A H'FF2B H'FF2E H'FF2C H'FF2D H'FF2F 1 H'FF30 H'FF31 H'FF32 H'FF33 H'FF36 H'FF34 H'FF35 H'FF37 H'FF38 H'FF39 H'FF3A H'FF3B H'FF3E H'FF3C ...
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Table 8-3 DMAC Registers (cont) Group Channel Address H'FF40 H'FF41 H'FF42 H'FF43 H'FF46 H'FF44 H'FF45 H'FF47 H'FF48 H'FF49 H'FF4A H'FF4B H'FF4E H'FF4C H'FF4D H'FF4F 3 H'FF50 H'FF51 H'FF52 H'FF53 H'FF56 H'FF54 H'FF55 H'FF57 H'FF58 H'FF59 H'FF5A H'FF5B H'FF5E ...
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Register Descriptions (1) (Short Address Mode) In short address mode, transfers can be carried out independently on channels A and B. Short address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA) as ...
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Memory Address Registers (MAR) A memory address register (MAR 32-bit readable/writable register that specifies a source or destination address. The transfer direction is determined automatically from the activation source. An MAR consists of four 8-bit registers designated ...