HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 324

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.6 Timer Output Control Register (TOCR)
TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels.
The settings of the XTGD, OLS4, and OLS3 bits are valid only in complementary PWM mode
and reset-synchronized PWM mode. These settings do not affect other modes.
TOCR is initialized to H'FF by a reset and in standby mode.
Bits 7 to 5—Reserved: Read-only bits, always read as 1.
Bit 4—External Trigger Disable (XTGD): Selects externally triggered disabling of ITU output
in complementary PWM mode and reset-synchronized PWM mode.
Bit 4
XTGD
0
1
Bit
Initial value
Read/Write
Description
Input capture A in channel 1 is used as an external trigger signal in complementary PWM
mode and reset-synchronized PWM mode.
When an external trigger occurs, bits 5 to 0 in the timer output master enable register
(TOER) are cleared to 0, disabling ITU output.
External triggering is disabled
—
—
7
1
Reserved bits
—
—
6
1
External trigger disable
Selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized
PWM mode
—
—
5
1
304
XTGD
R/W
4
1
Reserved bits
—
—
3
1
—
—
Output level select 3, 4
These bits select output
levels in complementary
PWM mode and reset-
synchronized PWM mode
2
1
OLS4
R/W
1
1
(Initial value)
OLS3
R/W
0
1