HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 363

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clearing Procedure for Complementary PWM Mode: Figure 10-34 shows the steps to clear
complementary PWM mode. First, (1) set combination mode (CMD) 1 and 0 bits in the timer
function control register (TFCR) from 10 back to 00 or 01, to switch from complementary PWM
mode to normal operating mode. Next, (2) wait at least one period of the counter input clock used
by channels 3 and 4, then clear counter start (STR) 3 and 4 bits in the timer start register (TSTR)
to stop operation of counters TCNT3 and TCNT4 in channels 3 and 4.
If a procedure other than that described above is used to clear complementary PWM mode, the
output waveform may not change according to the setting when complementary PWM mode is set
again.
Complementary PWM mode
Figure 10-34 Clearing Procedure for Complementary PWM Mode
Normal operating mode
Clear complementary
Stop couating
PWM mode
1
2
343
1. Clear the CMD1 bit of TFCR to 0 to
2. After setting channels 3 and 4 to
set channels 3 and 4 to normal
operating mode.
normal operating mode, wait at least
one counter clock period, then clear
bits STR3 and STR4 of TSTR to 0 to
stop counter operation of TCNT3 and
TCNT4.