HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 405

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.2 Register Descriptions
11.2.1 Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that selects input or output for each pin in port A.
Port A is multiplexed with pins TP
be set to 1. For further information about PADDR, see section 9.8, Port A.
11.2.2 Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when
these TPC output groups are used.
For further information about PADR, see section 9.8, Port A.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Note:
*
Bits selected for TPC output by NDERA settings become read-only bits.
PA DDR
R/(W)
PA
7
W
7
0
0
7
7
*
PA DDR
R/(W)
PA
6
W
0
6
0
6
6
*
7
to TP
PA DDR
R/(W)
PA
5
W
0
5
0
5
0
. Bits corresponding to pins used for TPC output must
5
*
Port A data direction 7 to 0
These bits select input or
output for port A pins
Port A data 7 to 0
These bits store output data
for TPC output groups 0 and 1
PA DDR
385
R/(W)
PA
4
W
4
0
0
4
4
*
PA DDR
R/(W)
PA
3
W
3
0
0
3
3
*
PA DDR
R/(W)
PA
2
W
0
2
0
2
2
*
PA DDR
R/(W)
PA
1
W
0
1
0
1
1
*
PA DDR
R/(W)
PA
0
W
0
0
0
0
0
*