HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 327

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When a general register is used as an input capture register, rising edges, falling edges, or both
edges of an external input capture signal are detected and the current TCNT value is stored in the
general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The
valid edge or edges of the input capture signal are selected in TIOR.
TIOR settings are ignored in PWM mode, complementary PWM mode, and reset-synchronized
PWM mode.
General registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word access or byte access.
General registers are initialized to the output compare function (with no output signal) by a reset
and in standby mode. The initial value is H'FFFF.
10.2.9 Buffer Registers (BRA, BRB)
The buffer registers are 16-bit registers. The ITU has four buffer registers, two each in channels 3
and 4.
Channel
3
4
A buffer register is a 16-bit readable/writable register that is used when buffering is selected.
Buffering can be selected independently by bits BFB4, BFA4, BFB3, and BFA3 in TFCR.
The buffer register and general register operate as a pair. When the general register functions as an
output compare register, the buffer register functions as an output compare buffer register. When
the general register functions as an input capture register, the buffer register functions as an input
capture buffer register.
Bit
Initial value
Read/Write
Abbreviation
BRA3, BRB3
BRA4, BRB4
R/W
15
1
R/W
14
1
R/W
13
1
Function
Used for buffering
• When the corresponding GRA or GRB functions as an output
• When the corresponding GRA or GRB functions as an input
compare register, BRA or BRB can function as an output compare
buffer register: the BRA or BRB value is automatically transferred
to GRA or GRB at compare match
capture register, BRA or BRB can function as an input capture
buffer register: the GRA or GRB value is automatically transferred
to BRA or BRB at input capture
R/W
12
1
R/W
11
1
R/W
10
1
R/W
307
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1