HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 289

MCU 5V 0K PB-FREE 112-QFP

HD6413003TF16V

Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413003TF16V

Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6413003TF16V
Manufacturer:
ITT
Quantity:
12 000
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS
Quantity:
36
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select
input or output for each pin in port B.
A pin in port B becomes an output pin if the corresponding PBDDR bit is set to 1, and an input
pin if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting, so if a PBDDR bit is set to 1, the corresponding pin maintains its
output state in software standby mode.
Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores data for
pins PB
When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is
returned directly. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin
level is read.
PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
7
to PB
0
.
PB DDR
PB
R/W
7
W
7
0
0
7
7
PB DDR
R/W
PB
6
W
0
6
0
6
6
PB DDR
R/W
PB
5
W
0
5
0
5
Port B data direction 7 to 0
These bits select input or output for port B pins
5
Port B data 7 to 0
These bits store data for port B pins
PB DDR
269
PB
R/W
4
W
4
0
0
4
4
PB DDR
PB
R/W
3
W
3
0
0
3
3
PB DDR
PB
R/W
2
W
0
2
0
2
2
PB DDR
R/W
PB
1
W
0
1
0
1
1
PB DDR
PB
R/W
0
W
0
0
0
0
0

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