HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 531

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.1 Overview
The H8/3003 has a power-down state that greatly reduces power consumption by halting CPU
functions. The power-down state includes the following three modes:
•
•
•
Table 17-1 indicates the methods of entering and exiting these power-down modes and the status
of the CPU and on-chip supporting modules in each mode.
Table 17-1 Power-Down State
Mode
Sleep
mode
Software
standby
mode
Hardware Low input at
standby
mode
Notes: 1. The refresh timer counter (RTCNT) and bits 7 and 6 of the refresh timer control/status register (RTMCSR) are
Legend
SYSCR: System control register
SSBY:
Sleep mode
Software standby mode
Hardware standby mode
2. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware
Software standby bit
initialized. Other bits and registers hold their previous states.
standby mode.
Entering
Conditions
SLEEP instruc- Active
tion executed
while SSBY = 0
in SYSCR
SLEEP instruc- Halted Halted Held
tion executed
while SSBY = 1
in SYSCR
STBY pin
Clock
Halted Halted Undeter
Section 17 Power-Down State
CPU
Halted Held
CPU
Registers DMAC Controller Functions RAM
mined
Active
Halted Halted
and
reset
Halted Halted
and
reset
511
Refresh
Active
and
held
and
reset
State
*1
Supporting
Active
Halted
and
reset
Halted
and
reset
Held
Held
Held
*2
I/O
Ports
Held
Held
High
impedance • RES
Exiting
Conditions
• Interrupt
• RES
• STBY
• NMI
• IRQ
• RES
• STBY
• STBY
0
to IRQ
2