HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 287

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9-14 Port A Pin Functions (cont)
Pin
PA
TEND
PA
TEND
1
0
/TP
/TP
1
0
1
0
/TCLKB/
/TCLKA/
Pin Functions and Selection Method
DMAC channel 1 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR1A and
DTCR1B), bit NDER1 in NDERA, and bit PA
function as follows
Note: * TCLKB input when MDF = 1 in TMDR, or when TPSC2 = 1,
DMAC channel 0 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR0A and
DTCR0B), bit NDER0 in NDERA, and bit PA
function as follows
Note: * TCLKA input when MDF = 1 in TMDR, or when TPSC2 = 1 and
DMAC channel
1 settings
PA
NDER1
Pin function
DMAC channel
1 settings
DTS2A, DTS1A
DTS0A
DTS2B
DTS1B
DMAC channel
0 settings
PA
NDER0
Pin function
DMAC channel
0 settings
DTS2A, DTS1A
DTS0A
DTS2B
DTS1B
1
0
DDR
DDR
TPSC1 = 0, and TPSC0 = 1 in any of TCR4 to TCR0.
TPSC1 = 0 in any of TCR4 to TCR0.
—
—
0
0
Not both 1
Not both 1
2
2
1 in table below
1 in table below
TEND
TEND
267
—
—
1
0
1
0
—
—
—
—
1
0
output
output
1
1
1
1
1
1
TCLKB input*
TCLKA input*
—
—
2
2
0
0
0
0
1
0
DDR in PADDR select the pin
DDR in PADDR select the pin
input
input
—
—
1
1
PA
0
1
PA
0
1
—
—
0
0
1
0
2 in table below
2 in table below
Both 1
Both 1
—
—
1
0
1
0
output
output
PA
PA
2
2
1
0
1
0
1
0
1
1
0
1
1
0
output
output
TP
TP
1
1
1
1
1
1
1
1
1
1
1
1
1
0