HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 33

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1-3 Pin Functions (cont)
Type
Refresh
controller
DMA
controller
(DMAC)
16-bit
integrated
time unit
(ITU)
Symbol
RFSH
CS
RD
HWR
LWR
DREQ
DREQ
TEND
TEND
TCLKD to
TCLKA
TIOCA
TIOCA
TIOCB
TIOCB
TOCXA
TOCXB
3
3
0
3
0
4
0
4
0
to
4
4
to
to
to
Pin No.
QFP-112
100
101
78
79
80
16, 14
9, 8
15, 13,
106, 105
108 to 105 Input
4, 2, 111,
109, 107
5, 3, 112,
110, 108
6
7
I/O
Output Refresh: Indicates a refresh cycle
Output Row address strobe
Output Column address strobe CAS: Column
Output Upper write: Write enable signal for DRAM
Output Lower write: Write enable signal for DRAM
Input
Output Transfer end 3 to 0: These signals indicate
Input/
output
Input/
output
Output Output compare XA4: PWM output
Output Output compare XB4: PWM output
13
Name and Function
strobe signal for DRAM connected to area 3
address strobe signal for bit DRAM connected
to area 3; used with 2WE DRAM.
Write enable: Write enable signal for DRAM
connected to area 3; used with 2CAS DRAM.
connected to area 3; used with 2WE DRAM.
Upper column address strobe: Column
address strobe signal for DRAM connected to
area 3; used with 2CAS DRAM.
connected to area 3; used with 2WE DRAM.
Lower column address strobe: Column
address strobe signal for DRAM connected to
area 3; used with 2CAS DRAM.
DMA request 3 to 0: DMAC activation
requests
that the DMAC has ended a data transfer
Clock input A to D: External clock inputs
Input capture/output compare A4 to A0:
GRA4 to GRA0 output compare or input
capture, or PWM output
Input capture/output compare B4 to B0:
GRB4 to GRB0 output compare or input
capture, or PWM output
RAS: Row address