HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 151

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 6-19 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state-access area. There is a minimum interval of two states from when the
BREQ signal goes low until the bus is released.
Figure 6-19 External-Bus-Released State (Two-State-Access Area, During Read Cycle)
ø
Address
Data bus
(D
AS
HWR
BREQ
BACK
1
2
3
4, 5
6
15
,
to D )
RD
Low
BACK
BREQ
High
BREQ
,
LWR
0
BREQ
BREQ
signal goes low at end of CPU read cycle, releasing bus right to external bus master.
pin continues to be sampled while bus is released to external bus master.
signal goes high, ending bus-release cycle.
High
signal is sampled twice consecutively.
signal is sampled at rise of T state.
T
0
1
CPU cycles
Minimum 2 cycles
T
1
Address
T
0
2
2
131
3
External bus released
High-impedance
High-impedance
High-impedance
High-impedance
4
5
6
CPU cycles