HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 163

MCU 5V 0K PB-FREE 112-QFP

HD6413003TF16V

Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413003TF16V

Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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7.2.3 Refresh Timer Counter (RTCNT)
RTCNT is an 8-bit readable/writable up-counter.
RTCNT is an up-counter that is incremented by an internal clock selected by bits CKS2 to CKS0
in RTMCSR. When RTCNT matches RTCOR (compare match), the CMF flag is set to 1 and
RTCNT is cleared to H'00.
RTCNT is write-disabled when the PSRAME bit or DRAME bit is set to 1. RTCNT is initialized
to H'00 by a reset and in standby mode.
7.2.4 Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit readable/writable register that determines the interval at which RTCNT is
cleared.
RTCOR and RTCNT are constantly compared. When their values match, the CMF flag is set to 1
in RTMCSR, and RTCNT is simultaneously cleared to H'00.
RTCOR is write-disabled when the PSRAME bit or DRAME bit is set to 1. RTCOR is initialized
to H'FF by a reset and in hardware standby mode. In software standby mode it retains its previous
value.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
R/W
R/W
7
0
7
1
R/W
R/W
6
0
6
1
R/W
R/W
5
0
5
1
143
R/W
R/W
4
0
4
1
R/W
R/W
3
0
3
1
R/W
R/W
2
0
2
1
R/W
R/W
1
0
1
1
R/W
R/W
0
0
0
1

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