DF36037FZJV Renesas Electronics America, DF36037FZJV Datasheet - Page 94

• Manufacturer Part Number: DF36037FZJV
• Description: MCU 3/5V 56K PB-FREE J-TEMP 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36037FZJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 3 Exception Handling
3.4
3.4.1
As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts.
NMI Interrupt: NMI interrupt is requested by input signal edge to pin NMI. This interrupt is
detected by either rising edge sensing or falling edge sensing, depending on the setting of bit
NMIEG in IEGR1.
NMI is the highest-priority interrupt, and can always be accepted without depending on the I bit
value in CCR.
IRQ3 to IRQ0 Interrupts: IRQ3 to IRQ0 interrupts are requested by input signals to pins IRQ3
to IRQ0. These four interrupts are given different vector addresses, and are detected individually
by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG3 to
IEG0 in IEGR1.
When pins IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal
edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt. These
interrupts can be masked by setting bits IEN3 to IEN0 in IENR1.
WKP5 to WKP0 Interrupts: WKP5 to WKP0 interrupts are requested by input signals to pins
WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected
individually by either rising edge sensing or falling edge sensing, depending on the settings of bits
WPEG5 to WPEG0 in IEGR2.
When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated signal
edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. These
interrupts can be masked by setting bit IENWP in IENR1.
Rev. 4.00 Mar. 15, 2006 Page 60 of 556
REJ09B0026-0400
Interrupt Exception Handling
External Interrupts