DF36037FZJV Renesas Electronics America, DF36037FZJV Datasheet - Page 336

• Manufacturer Part Number: DF36037FZJV
• Description: MCU 3/5V 56K PB-FREE J-TEMP 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36037FZJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.4
GSR indicates the status of the CAN bus. Each bit in GSR is set or cleared to notify the CPU of
the TinyCAN status.
Rev. 4.00 Mar. 15, 2006 Page 302 of 556
REJ09B0026-0400
Bit
7, 6
5
4
3
Bit Name
—
ERPS
HALT
RESET
General Status Register (GSR)
Initial
Value
All 0
0
0
1
R/W
—
R
R
R
Description
Reserved
These bits are always read as 0.
Error Passive Status Flag
Indicates whether the CDLC is in the error-passive state.
This flag is always set to 1 when the CDLC is in the error-
passive state or bus off state.
[Setting condition]
When TEC
[Clearing condition]
When the error-active state is entered
Indicates whether the TinyCAN is in halt mode.
[Setting condition]
When the CAN bus receives an intermission frame or the
bus is idle with the HLTRQ bit in MCR set to 1
[Clearing condition]
When the HLTRQ bit is cleared to 0 and halt mode is
exited
Reset Status Flag
Indicates whether the TinyCAN is in reset mode.
[Setting condition]
When the TinyCAN is in the reset state
[Clearing condition]
When communication with the CAN bus is enabled after
the reset procedure completes
Halt Status Flag
128 or REC
128