DF36037FZJV Renesas Electronics America, DF36037FZJV Datasheet - Page 306

• Manufacturer Part Number: DF36037FZJV
• Description: MCU 3/5V 56K PB-FREE J-TEMP 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36037FZJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Serial Communication Interface 3 (SCI3)
14.4.3
Figure 14.5 shows an example of operation for transmission in asynchronous mode. In
transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that
2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts
3. The SCI3 checks the TDRE flag at the timing for sending the stop bit.
4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
6. Figure 14.6 shows a sample flowchart for transmission in asynchronous mode.
Rev. 4.00 Mar. 15, 2006 Page 272 of 556
REJ09B0026-0400
data has been written to TDR, and transfers the data from TDR to TSR.
transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated.
Continuous transmission is possible because the TXI interrupt routine writes next transmit data
to TDR before transmission of the current transmit data has been completed.
serial transmission of the next frame is started.
state” is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI
interrupt request is generated.
Serial
data
TDRE
TEND
LSI
operation
User
processing
Data Transmission
Figure 14.5 Example of SCI3 Transmission in Asynchronous Mode
TXI interrupt
request
generated
1
Start
bit
0
D0
D1
TDRE flag
cleared to 0
Data written
to TDR
Transmit
1 frame
(8-Bit Data, Parity, One Stop Bit)
data
D7
Parity
0/1
bit
TXI interrupt request generated
Stop
bit
1
Start
bit
0
D0
1 frame
D1
Transmit
data
D7
Parity
0/1
bit
TEI interrupt request
generated
Stop
bit
1
Mark
state
1