DF36037FZJV Renesas Electronics America, DF36037FZJV Datasheet - Page 12

• Manufacturer Part Number: DF36037FZJV
• Description: MCU 3/5V 56K PB-FREE J-TEMP 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36037FZJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.3
3.4
3.5
Section 4 Address Break ..................................................................................... 67
4.1
4.2
Section 5 Clock Pulse Generators ....................................................................... 73
5.1
5.2
5.3
Section 6 Power-Down Modes............................................................................ 77
6.1
Rev. 4.00 Mar. 15, 2006 Page x of xxxii
3.2.4
3.2.5
3.2.6
3.2.7
Reset Exception Handling .................................................................................................. 59
Interrupt Exception Handling ............................................................................................. 60
3.4.1
3.4.2
3.4.3
3.4.4
Usage Notes ........................................................................................................................ 65
3.5.1
3.5.2
3.5.3
Register Descriptions.......................................................................................................... 68
4.1.1
4.1.2
4.1.3
4.1.4
Operation ............................................................................................................................ 71
System Clock Generator ..................................................................................................... 74
5.1.1
5.1.2
5.1.3
Prescaler.............................................................................................................................. 76
5.2.1
Usage Notes ........................................................................................................................ 76
5.3.1
5.3.2
Register Descriptions.......................................................................................................... 78
6.1.1
6.1.2
6.1.3
6.1.4
Interrupt Enable Register 2 (IENR2) .................................................................. 55
Interrupt Flag Register 1 (IRR1)......................................................................... 55
Interrupt Flag Register 2 (IRR2)......................................................................... 57
Wakeup Interrupt Flag Register (IWPR) ............................................................ 57
External Interrupts .............................................................................................. 60
Internal Interrupts ............................................................................................... 61
Interrupt Handling Sequence .............................................................................. 62
Interrupt Response Time..................................................................................... 63
Interrupts after Reset........................................................................................... 65
Notes on Stack Area Use .................................................................................... 65
Notes on Rewriting Port Mode Registers ........................................................... 65
Address Break Control Register (ABRKCR) ..................................................... 68
Address Break Status Register (ABRKSR) ........................................................ 70
Break Address Registers (BARH, BARL).......................................................... 70
Break Data Registers (BDRH, BDRL) ............................................................... 70
Connecting Crystal Resonator ............................................................................ 74
Connecting Ceramic Resonator .......................................................................... 75
External Clock Input Method.............................................................................. 75
Prescaler S .......................................................................................................... 76
Note on Resonators............................................................................................. 76
Notes on Board Design ....................................................................................... 76
System Control Register 1 (SYSCR1) ................................................................ 78
System Control Register 2 (SYSCR2) ................................................................ 79
Module Standby Control Register 1 (MSTCR1) ................................................ 80
Module Standby Control Register 2 (MSTCR2) ................................................ 81