DF36037FZJV Renesas Electronics America, DF36037FZJV Datasheet - Page 29

• Manufacturer Part Number: DF36037FZJV
• Description: MCU 3/5V 56K PB-FREE J-TEMP 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36037FZJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 19.4 Operational Timing of LVDI Circuit....................................................................... 411
Figure 19.5 Timing for Operation/Release of Low-Voltage Detection Circuit .......................... 412
Section 20 Power Supply Circuit
Figure 20.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 413
Figure 20.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 414
Section 22 Electrical Characteristics
Figure 22.1 System Clock Input Timing..................................................................................... 478
Figure 22.2 RES Low Width Timing.......................................................................................... 478
Figure 22.3 Input Timing............................................................................................................ 478
Figure 22.4 SCK3 Input Clock Timing....................................................................................... 479
Figure 22.5 SCI Input/Output Timing in Clocked Synchronous Mode ...................................... 479
Figure 22.6 TinyCAN Input/Output Timing............................................................................... 480
Figure 22.7 SSU Input/Output Timing in Clocked Synchronous Mode ..................................... 480
Figure 22.8 SSU Input/Output Timing
Figure 22.9 SSU Input/Output Timing
Figure 22.10 SSU Input/Output Timing
Figure 22.11 SSU Input/Output Timing
Figure 22.12 Output Load Circuit............................................................................................... 485
Appendix B I/O Port Block Diagrams
Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 517
Figure B.2 Port 1 Block Diagram (P14, P16) ............................................................................. 518
Figure B.3 Port 1 Block Diagram (P15) ..................................................................................... 519
Figure B.4 Port 1 Block Diagram (P12, P11, P10) ..................................................................... 520
Figure B.5 Port 2 Block Diagram (P24, P23) ............................................................................. 521
Figure B.6 Port 2 Block Diagram (P22) ..................................................................................... 522
Figure B.7 Port 2 Block Diagram (P21) ..................................................................................... 523
Figure B.8 Port 2 Block Diagram (P20) ..................................................................................... 524
Figure B.9 Port 5 Block Diagram (P57, P56) ............................................................................. 525
Figure B.10 Port 5 Block Diagram (P55) ................................................................................... 526
Figure B.11 Port 5 Block Diagram (P54 to P55) ........................................................................ 527
Figure B.12 Port 6 Block Diagram (P67 to P60) ........................................................................ 528
Figure B.13 Port 7 Block Diagram (P76) ................................................................................... 529
Figure B.14 Port 7 Block Diagram (P75) ................................................................................... 530
Figure B.15 Port 7 Block Diagram (P74) ................................................................................... 531
Figure B.16 Port 7 Block Diagram (P72) ................................................................................... 532
(Four-Line Bus Communication Mode, Master, CPHS = 1) ................................... 481
(Four-Line Bus Communication Mode, Master, CPHS = 0) ................................... 482
(Four-Line Bus Communication Mode, Slave, CPHS = 1) ................................... 483
(Four-Line Bus Communication Mode, Slave, CPHS = 0) ................................... 484
Rev. 4.00 Mar. 15, 2006 Page xxvii of xxxii