DF36037FZJV Renesas Electronics America, DF36037FZJV Datasheet - Page 70

MCU 3/5V 56K PB-FREE J-TEMP 64-L

DF36037FZJV

Manufacturer Part Number
DF36037FZJV
Description
MCU 3/5V 56K PB-FREE J-TEMP 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of DF36037FZJV

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 2 CPU
2.5.2
Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI,
the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address.
Table 2.12 Effective Address Calculation (1)
Rev. 4.00 Mar. 15, 2006 Page 36 of 556
REJ09B0026-0400
Register indirect with post-increment or
pre-decrement
•Register indirect with post-increment @ERn+
•Register indirect with pre-decrement @-ERn
Register direct(Rn)
Register indirect(@ERn)
Addressing Mode and Instruction Format
Effective Address Calculation
The value to be added or subtracted is 1 when the
operand is byte size, 2 for word size, and 4 for
longword size.
Sign extension
Effective Address Calculation
General register contents
General register contents
General register contents
General register contents
1, 2, or 4
1, 2, or 4
Operand is general register contents.
Effective Address (EA)

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