DF36037FZJV Renesas Electronics America, DF36037FZJV Datasheet - Page 65
![MCU 3/5V 56K PB-FREE J-TEMP 64-L](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36037FZJV
Manufacturer Part Number
DF36037FZJV
Description
MCU 3/5V 56K PB-FREE J-TEMP 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36037FZJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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2.4.2
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.7 shows examples of instruction formats.
Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit
address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).
Condition Field
Specifies the branching condition of Bcc instructions.
Basic Instruction Formats
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
op
op
op
Figure 2.7 Instruction Formats
cc
EA(disp)
op
r n
r n
EA(disp)
r m
r m
Rev. 4.00 Mar. 15, 2006 Page 31 of 556
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm
BRA d:8
REJ09B0026-0400
Section 2 CPU
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