R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 484

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
0.20
REVISION HISTORY
Jun 28, 2006
Date
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14.3.12 Notes on Timer RD;
14.3.12.1 TRDSTR Register (i = 0 or 1) added.
14.3.12.6 Reset Synchronous PWM Mode revised.
14.3.12.7 Complementary PWM Mode revised.
14.3.13.7 PWM3 mode deleted.
14.3.12.8 Count Source fOCO40M added.
14.4 Timer RE, on the 3rd line;
14.4.2 Notes on Timer RE;
Figure 15.5 Registers UiC0 and UiC1 (i = 0 or 1);
Table 15.5 Registers Used and Settings for UART Mode revised.
Table 15.6 I/O Pin Functions in UART Mode revised.
Figure 15.10 Transmit Timing in UART Mode revised.
Figure 15.11 Receive Timing Example in UART Mode revised.
15.3 Notes on Serial Interface;
16. Clock Synchronous Serial Interface, on the 3rd line;
16.2 Clock Synchronous Serial I/O with Chip Select (SSU);
Table 16.2 Clock Synchronous Serial I/O with Chip Select Specifications;
Figure 16.4 SSMR Register revised.
Figure 16.7 SSMR2 Register revised.
Figure 16.8 Registers SSTDR and SSRDR;
16.2.1 Transfer Clock;
16.2.5.2 Data Transmission;
16.2.5.2 Data Transmission, on the 4th line from the bottom;
Figure 16.14 Sample Flowchart of Data Transmission (Clock Synchronous
Communication Mode);
16.2.5.3 Data Reception;
R8C/20 Group, R8C/21 Group Hardware Manual
“14.3.13 Precautions on Timer RD” → “14.3.12 Notes on Timer RD”
revised.
“The count source ~ timer operations.” added.
“14.4.2 Precautions on Timer RE” → “14.4.2 Notes on Timer RE” revised.
The UiC0 register (i=0 or 1) revised.
“15.3 Precautions on Serial Interface” → “15.3 Notes on Serial Interface”
revised.
“(SSU)” added.
“(SSU)” added.
NOTE2 deleted.
NOTE in the SSTDR register revised.
“φ” → “f1” revised.
“16.2.5.2 Data Transmit” → “16.2.5.2 Data Transmission” revised.
“When setting the ~ transmit is enabled.” deleted.
NOTE revised.
“16.2.5.3 Data Receive” → “16.2.5.3 Data Reception” revised.
C - 8
Description
Summary