R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 185

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 14.31
14.3.3
• The IOA2 to IOA0 bits in the TRDIORA0 register are set to 100b.
• The CMD1 to CMD0 bits in the TRDFCR register are set to 00b.
The above applies to the following conditions:
• The SYNC bit in the TRDMR register is set to 1 (synchronous operation).
• The CCLR2 to CCLR0 bits in the TRDCR0 register are set to 001b (set the TRD0 register to 0000h in input capture).
The PWM 3 bit in the TRDFCR register is set to 1.
The CCLR2 to CCLR0 bits in the TRDCR1 register are set to 011b.
(Set the TRD1 register to 0000h synchronizing with the TRD0 register.)
The TRD1 register is synchronized with the TRD0 register.
TRDIOA0 input
• Synchronous preset
• Synchronous clear
TRD0 register
TRD1 register
When the SYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both
the TRD0 and TRD1 registers after writing to the TRDi register.
When the SYNC bit in the TRDMR register is set to 1 and the CCLR2 to CCLR0 bits in the TRDCRi
register are set to 011b (synchronous clear), and the TRD0 register is set to 0000h at the same time as the
TRD1 register is set to 0000h.
Also, when the SYNC bit in the TRDMR register is set to 1 and the CCLR2 to CCLR0 bits in the TRDCRi
register are set to 011b (synchronous clear), and the TRD1 register is set to 0000h at the same time as the
TRD0 register is set to 0000h.
Synchronous Operation
Value in
Value in
Synchronous Operation
n
n
Page 167 of 458
n writing
n is set
n is set
Set to 0000h with TRD0 register
Set to 0000h by input capture
(Input capture at the rising edge of the TRDIOA0 input)
14. Timers