R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 479
![MCU FLASH 96K 5K CMOS 48-LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F2121AJFP#U0
Manufacturer Part Number
R5F2121AJFP#U0
Description
MCU FLASH 96K 5K CMOS 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/21r
Datasheet
1.R5F21216JFP.pdf
(503 pages)
Specifications of R5F2121AJFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Rev.
0.20
REVISION HISTORY
Jun 28, 2006
Date
51 to 61 7.4 Port Settings added.
Page
35
42
43
45
47
49
63
64
67
69
70
71
72
73
74
75
6.1 VCC Input Voltage;
Figure 7.2 Configuration of Programmable I/O Ports (2) revised.
Figure 7.3 Configuration of Programmable I/O Ports (3) revised.
Figure 7.5 Configuration of Programmable I/O Ports (5) revised.
Figure 7.7 Configuration of Programmable I/O Ports (7) revised.
Figure 7.9 PDi (i = 0 to 4 and 6) Registers;
Figure 7.10 Pi (i = 0 to 4 and 6) Registers;
8.1 Processor Modes
9. Bus revised;
Table 9.2 Bus Cycles by Access Space of the R8C/21 Group added.
Table 9.3 Access Unit and Bus Operations;
Figure 10.2 CM0 Register;
Figure 10.4 OCD Register;
Figure 10.5 Registers FRA0 and FRA1;
Figure 10.7 VCA2 Register added.
Figure 10.8 Examples of XIN Clock Connection Circuit;
10.2.2 High-Speed On-Chip Oscillator Clock, on the 3rd and 8th lines;
10.3.5 fOCO40M;
Table 10.2 Settings and Modes of Clock Associated Bits;
R8C/20 Group, R8C/21 Group Hardware Manual
“6.1 Monitoring VCC Input Voltage” → “6.1 VCC Input Voltage”
revised.
NOTE3 added.
P6 Address “00EEh” → “00ECh” corrected.
“8.1 Type of Processor Mode” → “8.1 Processor Modes” revised.
“SFR” → “SFR, data flash”
“ROM/RAM” → “ROM (program ROM), RAM”
below the Table.9.3
“However, only following ~ at a time.” added.
NOTE6 deleted.
“System clock select bet(3)” → “System clock select bet(4)”
“1:Selects on-chip oscillator clock(4)” → “1:Selects on-chip oscillator
clock(3)” corrected.
NOTE2 in the FRA0 register revised.
NOTE revised.
“To use the high-speed ~ (divide-by-4 mode or more).” added.
“Since the difference ~ each bit” → “Since there are ~ individual bits.”
revised.
“fOCO40M can be used with supply voltage VCC = 3.0 to 5.5V.”
added.
“-: can be 0 or 1, no change in outcome.” added.
C - 3
Description
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