R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 174

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 14.25
14.2.5.2
The following three workarounds should be performed in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
•
•
(2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize
•
When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
Workaround example (a):
As shown in Figure 14.25, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These
write operations must be completed by the beginning of period A.
following points:
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 14.25 and 14.26.
The following shows the detailed workaround examples.
Programmable waveform generation mode
Workaround Example (a) When Timer RB Interrupt is Used
TRBO pin output
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
underflow signal
varies depending on the instruction being executed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
TRBIC register
Count source/
Interrupt request
is generated
prescaler
Page 156 of 458
IR bit in
(a)
sequence
Interrupt
(b)
Primary period
Interrupt request is
acknowledged
interrupt routine
Instruction in
Set the secondary and then
the primary register immediately
Ensure sufficient time
Secondary period
Period A
14. Timers