R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 219

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Table 14.27
i = 0 or 1, j = either B, C or D,
h = either A, B, C or D
Count Sources
Count Operations
PWM Waveform
Count Start Condition
Count Stop Conditions
Interrupt Request Generation
Timing
TRDIOA0 Pin Function
TRDIOA1 Pin Function
TRDIOB0, TRDIOC0, TRDIOD0,
TRDIOB1, TRDIOC1, TRDIOD1
Pin Functions
INT0 Pin Function
Read from Timer
Write to Timer
Selection Functions
PWM Mode Specifications
Item
Page 201 of 458
f1, f2, f4, f8, f32, fOCO40M
Write 1 (count starts) to the TSTARTi bit in the TRDSTR register.
• Write 0 (count stops) to the TSTARTi bit in the TRDSTR register
The count value can be read by reading the TRDi register.
The value can be written to the TRDi register.
External signal input to the TRDCLK pin (valid edge selected by a
program)
Increment
PWM period: 1/fk x (m+1)
Active level width: 1/fk x (m-n)
Inactive level width: 1/fk x (n+1)
• The PWM output pin holds output level before the count stops.
• When the CSELi bit in the TRDSTR register is set to 0, the count
• The PWM output pin holds level after output change by the compare
• Compare match (the content in the TRDi register matches with the
• TRDi register overflows
Programmable I/O port or TRDCLK (external clock) input
Programmable I/O port
Programmable I/O port or pulse output (select every pin)
Programmable I/O port, pulse output forced cutoff signal input or INT0
interrupt input
• 1 to 3 PWM output pins selected per 1 channel
• Either 1 pin or multiple pins of the TRDIOBi, TRDIOCi or TRDIODi
• The active level selected every pin.
• Initial output level selected every pin.
• Synchronous operation (refer to 14.3.3 Synchronous Operation.)
• Buffer operation (refer to 14.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (refer to 14.3.4 Pulse Output
fk: Frequency of count source
m: Setting value in the TRDGRAi register
n: Setting value in the TRDGRji register
when the CSELi bit in the TRDSTR register is set to 1.
stops at the compare match in the TRDGRAi register.
match.
content in the TRDGRhi register.)
pin.
Forced Cutoff.)
n + 1
m + 1
m - n
Specification
(When “L” is selected for the active level)
14. Timers