AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 99

• Manufacturer Part Number: AT91M55800A-33CJ
• Description: IC ARM MCU 16BIT 176BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800A-33CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 58
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91EB55
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• Cpu Family: AT91
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 58
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: BGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.4
15.5
15.6
15.7
15.8
1745F–ATARM–06-Sep-07
Interrupt Masking
Interrupt Clearing and Setting
Fast Interrupt Request
Software Interrupt
Spurious Interrupt
Each interrupt source, including FIQ, can be enabled or disabled using the command registers
AIC_IECR and AIC_IDCR. The interrupt mask can be read in the Read-only register AIC_IMR. A
disabled interrupt does not affect the servicing of other interrupts.
All interrupt sources which are programmed to be edge-triggered (including FIQ) can be individ-
ually set or cleared by respectively writing to the registers AIC_ISCR and AIC_ICCR. This
function of the interrupt controller is available for auto-test or software debug purposes.
The external FIQ line is the only source which can raise a fast interrupt request to the processor.
Therefore, it has no priority controller.
The external FIQ line can be programmed to be positive or negative edge-triggered or high- or
low-level sensitive in the AIC_SMR0 register.
The fast interrupt handler address can be stored in the AIC_SVR0 register. The value written
into this register is available by reading the AIC_FVR register when an FIQ interrupt is raised. By
storing the following instruction at address 0x0000001C, the processor loads the program
counter with the interrupt handler address stored in the AIC_FVR register.
Alternatively, the interrupt handler can be stored starting from address 0x0000001C as
described in the ARM7TDMI datasheet.
Interrupt source 1 of the advanced interrupt controller is a software interrupt. It must be pro-
grammed to be edge-triggered in order to set or clear it by writing to the AIC_ISCR and
AIC_ICCR.
This is totally independent of the SWI instruction of the ARM7TDMI processor.
When the AIC asserts the NIRQ line, the ARM7TDMI enters IRQ mode and the interrupt handler
reads the IVR. It may happen that the AIC de-asserts the NIRQ line after the core has taken into
account the NIRQ assertion and before the read of the IVR.
This behavior is called a Spurious Interrupt.
The AIC is able to detect these Spurious Interrupts and returns the Spurious Vector when the
IVR is read. The Spurious Vector can be programmed by the user when the vector table is
initialized.
A Spurious Interrupt may occur in the following cases:
• With any sources programmed to be level sensitive, if the interrupt signal of the AIC input is
• If an interrupt is asserted at the same time as the software is disabling the corresponding
de-asserted at the same time as it is taken into account by the ARM7TDMI.
source through AIC_IDCR (this can happen due to the pipelining of the ARM Core).
ldr PC,[PC,# -&F20]
AT91M5880A
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