AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 190

IC ARM MCU 16BIT 176BGA

AT91M55800A-33CJ

Manufacturer Part Number
AT91M55800A-33CJ
Description
IC ARM MCU 16BIT 176BGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91M55800A-33CJ

Core Processor
ARM7
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
POR, WDT
Number Of I /o
58
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Processor Series
AT91Mx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
EBI, SPI, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
58
Number Of Timers
10 bit
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91EB55
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
8 bit, 2 Channel
Cpu Family
AT91
Device Core
ARM7TDMI
Device Core Size
32b
Frequency (max)
33MHz
Program Memory Size
Not Required
Total Internal Ram Size
8KB
# I/os (max)
58
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
176
Package Type
BGA
For Use With
AT91EB55 - KIT EVAL FOR ARM AT91M55800A
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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20. SPI: Serial Peripheral Interface
20.1
190
Pin Description
AT91M5880A
The AT91M55800A includes an SPI which provides communication with external devices in
master or slave mode.
The SPI has four external chip selects which can be connected to up to 15 devices. The data
length is programmable, from 8- to 16-bit.
As for the USART, a 2-channel PDC can be used to move data between memory and the SPI
without CPU intervention.
Seven pins are associated with the SPI Interface. When not needed for the SPI function, each of
these pins can be configured as a PIO.
Support for an external master is provided by the PIO Controller Multi-driver option. To configure
an SPI pin as open-drain to support external drivers, set the corresponding bits in the
PIO_MDSR register.
An input filter can be enabled on the SPI input pins by setting the corresponding bits in the
PIO_IFSR.
The NPCS0/NSS pin can function as a peripheral chip select output or slave select input. Refer
to
Figure 20-1. SPI Block Diagram
Table 20-1
APB
for a description of the SPI pins.
MCK
MCK/32
Serial Peripheral Interface
Interrupt Controller
Advanced
INT
NPCS0/NSS
NPCS1
NPCS2
NPCS3
SPCK
MISO
MOSI
Parallel IO
Controller
NPCS0/NSS
1745F–ATARM–06-Sep-07
NPCS1
NPCS2
NPCS3
SPCK
MISO
MOSI

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