AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 100

• Manufacturer Part Number: AT91M55800A-33CJ
• Description: IC ARM MCU 16BIT 176BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800A-33CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 58
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91EB55
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• Cpu Family: AT91
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 58
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: BGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.9
100
Protect Mode
AT91M5880A
The same mechanism of Spurious Interrupt occurs if the ARM7TDMI reads the IVR (application
software or ICE) when there is no interrupt pending. This mechanism is also valid for the FIQ
interrupts.
Once the AIC enters the Spurious Interrupt management, it asserts neither the NIRQ nor the
NFIQ lines to the ARM7TDMI as long as the Spurious Interrupt is not acknowledged. Therefore,
it is mandatory for the Spurious Interrupt Service Routine to acknowledge the “Spurious” behav-
ior by writing to the AIC_EOICR (End of Interrupt) before returning to the interrupted software. It
also can perform other operation(s), e.g. trace possible undesirable behavior.
The Protect Mode permits reading of the Interrupt Vector Register without performing the associ-
ated automatic operations. This is necessary when working with a debug system.
When a Debug Monitor or an ICE reads the AIC User Interface, the IVR could be read. This
would have the following consequences in normal mode:
In either case, an End of Interrupt Command would be necessary to acknowledge and to restore
the context of the AIC. This operation is generally not performed by the debug system. Hence
the debug system would become strongly intrusive, and could cause the application to enter an
undesired state.
This is avoided by using Protect Mode.
The Protect Mode is enabled by setting the AIC bit in the SF Protect Mode Register.
When Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is
performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data)
to the AIC_IVR just after reading it.
The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is
updated with the current interrupt only when IVR is written.
An AIC_IVR read on its own (e.g. by a debugger), modifies neither the AIC context nor the
AIC_ISR.
Extra AIC_IVR reads performed in between the read and the write can cause unpredictable
results. Therefore, it is strongly recommended not to set a breakpoint between these 2 actions,
nor to stop the software.
The debug system must not write to the AIC_IVR as this would cause undesirable effects.
• If an enabled interrupt with a higher priority than the current one is pending, it would be
• If there is no enabled pending interrupt, the spurious vector would be returned.
stacked.
1745F–ATARM–06-Sep-07