AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 61

IC ARM MCU 16BIT 176BGA

AT91M55800A-33CJ

Manufacturer Part Number
AT91M55800A-33CJ
Description
IC ARM MCU 16BIT 176BGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91M55800A-33CJ

Core Processor
ARM7
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
POR, WDT
Number Of I /o
58
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Processor Series
AT91Mx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
EBI, SPI, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
58
Number Of Timers
10 bit
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91EB55
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
8 bit, 2 Channel
Cpu Family
AT91
Device Core
ARM7TDMI
Device Core Size
32b
Frequency (max)
33MHz
Program Memory Size
Not Required
Total Internal Ram Size
8KB
# I/os (max)
58
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
176
Package Type
BGA
For Use With
AT91EB55 - KIT EVAL FOR ARM AT91M55800A
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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12.8
1745F–ATARM–06-Sep-07
First Start-up Sequence
At initial startup, or after VDDBU has been disconnected, the battery-supplied logic must be
initialized.
The Battery Backup Reset sets the following default state:
A simple RC network can be used as a power-on reset for the battery supply.
The pin SHDN is tri-stated by default. An external resistor must hold the main power supply
shut-down pin in the inactive state. The shut-down logic can be programmed with the correct
active level of the power supply shut-down input during the first start-up sequence.
The first time the system is powered up, the SHDN pin is tri-stated because different power sup-
plies use different logic levels for their shut-down input signals. To minimize backup battery
power consumption, there is no internal pull-up or pull-down on this signal.
If the power supply needs a logic level on its shut-down input in order to start the main power
supply then an external “Force Start Up” jumper is required to provide this level.
The jumper provides the necessary level on the SHDN to maintain the power supply when the
AT91 boots, and it can be removed until the next loss of battery power.
• Shut-down Logic
• The Power Mode Register
• The Real-time Clock Configuration and Data Registers
Initialized in the Wake-up state (or Non Alarm)
Shut-down defines SHDN as level 0 (SHDALS = 1)
Wake-up defines SHDN as tri-state (WKACKS = 0)
AT91M5880A
61

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