AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 140

• Manufacturer Part Number: AT91M55800A-33CJ
• Description: IC ARM MCU 16BIT 176BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800A-33CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 58
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91EB55
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• Cpu Family: AT91
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 58
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: BGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.6
18.6.1
140
Break
AT91M5880A
Transmit Break
A break condition is a low signal level which has a duration of at least one character (including
start/stop bits and parity).
The transmitter generates a break condition on the TXD line when STTBRK is set in US_CR
(Control Register). In this case, the character present in the Transmit Shift Register is completed
before the line is held low.
To cancel a break condition on the TXD line, the STPBRK command in US_CR must be set. The
USART completes a minimum break duration of one character length. The TXD line then returns
to high level (idle state) for at least 12-bit periods to ensure that the end of break is correctly
detected. Then the transmitter resumes normal operation.
The BREAK is managed like a character:
In order to avoid unpredictable states:
• The STTBRK and the STPBRK commands are performed only if the transmitter is ready (bit
• The STTBRK command blocks the transmitter holding register (bit TXRDY is cleared in
• A break is started when the Shift Register is empty (any previous character is fully
• STTBRK and STPBRK commands must not be requested at the same time
• Once an STTBRK command is requested, further STTBRK commands are ignored until the
• All STPBRK commands requested without a previous STTBRK command are ignored
• A byte written into the Transmit Holding Register while a break is pending but not started (bit
• It is not permitted to write new data in the Transmit Holding Register while a break is in
• A new STTBRK command must not be issued until an existing break has ended
TXRDY = 1 in US_CSR)
US_CSR) until the break has started
transmitted). US_CSR.TXEMPTY is cleared. The break blocks the transmitter shift register
until it is completed (high level for at least 12-bit periods after the STPBRK command is
requested)
BREAK is ended (high level for at least 12-bit periods)
TXRDY = 0 in US_CSR) is ignored
progress (STPBRK has not been requested), even though TXRDY = 1 in US_CSR.
(TXEMPTY=1 in US_CSR).
1745F–ATARM–06-Sep-07