AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 90

IC ARM MCU 16BIT 176BGA

AT91M55800A-33CJ

Manufacturer Part Number
AT91M55800A-33CJ
Description
IC ARM MCU 16BIT 176BGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91M55800A-33CJ

Core Processor
ARM7
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
POR, WDT
Number Of I /o
58
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Processor Series
AT91Mx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
EBI, SPI, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
58
Number Of Timers
10 bit
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91EB55
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
8 bit, 2 Channel
Cpu Family
AT91
Device Core
ARM7TDMI
Device Core Size
32b
Frequency (max)
33MHz
Program Memory Size
Not Required
Total Internal Ram Size
8KB
# I/os (max)
58
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
176
Package Type
BGA
For Use With
AT91EB55 - KIT EVAL FOR ARM AT91M55800A
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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14. WD: Watchdog Timer
Figure 14-1. Watchdog Timer Block Diagram
90
AT91M5880A
MCK/1024
MCK/4096
MCK/128
MCK/32
WD_RESET
Advanced
Bus (APB)
Peripheral
WDIRQ
The AT91M55800A has an internal Watchdog Timer that can be used to prevent system lock-up
if the software becomes trapped in a deadlock.
In normal operation the user reloads the watchdog at regular intervals before the timer overflow
occurs. If an overflow does occur, the watchdog timer generates one or a combination of the fol-
lowing signals, depending on the parameters in WD_OMR (Overflow Mode Register):
The watchdog timer has a 16-bit down counter. Bits 12 - 15 of the value loaded when the watch-
dog is restarted are programmable using the HPVC parameter in WD_CMR (Clock Mode). Four
clock sources are available to the watchdog counter: MCK/32, MCK/128, MCK/1024 or
MCK/4096. The selection is made using the WDCLKS parameter in WD_CMR. This provides a
programmable time-out period of 4 ms to 8 sec. with a 33 MHz system clock.
All write accesses are protected by control access keys to help prevent corruption of the watch-
dog should an error condition occur. To update the contents of the mode and control registers it
is necessary to write the correct bit pattern to the control access key bits at the same time as the
control bits are written (the same write access).
• If RSTEN is set, an internal reset is generated (WD_RESET as shown in Figure 14-1).
• If IRQEN is set, a pulse is generated on the signal WDIRQ which is connected to the
• If EXTEN is set, a low level is driven on the NWDOVF signal for a duration of 8 MCK cycles.
Advanced Interrupt Controller
Clock Select
Control Logic
CLK_CNT
Clear
Overflow
Programmable
Down Counter
16-Bit
NWDOVF
1745F–ATARM–06-Sep-07

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