AT91SAM9260B-CU-999 Atmel, AT91SAM9260B-CU-999 Datasheet - Page 772

• Manufacturer Part Number: AT91SAM9260B-CU-999
• Description: IC MCU ARM9 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9260B-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

43.3.6
43.3.6.1
43.3.6.2
43.3.7
43.3.7.1
772
AT91SAM9260
SDRAM Controller
Reset Controller (RSTC)
SDCLK Clock Active After Reset
Mobile SDRAM dEvice Initialization Constraint
RSTC: Reset during SDRAM Accesses
After a reset, the SDRAM clock is always active leading to over consumption in the pad.
The following sequence stops the SDRAM clock.
Using Mobile SDRAM devices that need to have their DQMx level HIGH during Mobile SDRAM
device initialization may lead to data bus contention and thus external memories on the same
EBI must not be accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “Don’t care” during this
phase.
Mobile SDRAM initialization must be performed in internal SRAM.
When a User Reset occurs during SDRAM read access, the SDRAM clock is turned off while
data is ready to be read on the data bus. The SDRAM maintains the data until the clock restarts.
If the User Reset is programmed to assert a general reset, the data maintained by the SDRAM
leads to a data bus conflict and adversely affects the boot memories connected on the EBI:
In the interrupt routine, power down the SDRAM properly and perform Peripheral and Processor
Reset with software in assembler.
Example with libV3.
1. Set the bit LPCB in the SDRAMC Low Power Register.
2. Write 0 in the SDRAMC Mode Register and perform a dummy write in SDRAM to
• NAND Flash boot functionality, if the system boots out of internal ROM.
• NOR Flash boot, if the system boots on an external memory connected on the EBI CS0.
1. Avoid User Reset to generate a system reset.
2. Trap the User Reset with an interrupt.
• The main code:
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
//user reset interrupt setting
complete.
// Configure AIC controller to handle SSC interrupts
AT91F_AIC_ConfigureIt (
AT91C_BASE_AIC,
AT91C_ID_SYS,
AT91C_AIC_PRIOR_HIGHEST,
AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED, // Level sensitive
sysc_handler );
// System peripheral ID
// AIC base address
// Max priority
6221I–ATARM–17-Jul-09