AT91SAM9260B-CU-999 Atmel, AT91SAM9260B-CU-999 Datasheet - Page 52

• Manufacturer Part Number: AT91SAM9260B-CU-999
• Description: IC MCU ARM9 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9260B-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.4.2
Figure 11-3. Application Test Environment Example
11.5
52
Debug and Test Pin Description
AT91SAM9260
Test Environment
Figure 11-3 on page 52
preted by the tester. In this example, the “board in test” is designed using a number of JTAG-
compliant devices. These devices can be connected to form a single scan chain.
Table 11-1.
Pin Name
NRST
TST
NTRST
TCK
TDI
TDO
TMS
RTCK
JTAGSEL
DRXD
DTXD
AT91SAM9260-based Application Board In Test
ICE/JTAG
Connector
Debug and Test Pin List
AT91SAM9260
Interface
JTAG
Chip n
shows a test environment example. Test vectors are sent and inter-
Test Adaptor
Function
Microcontroller Reset
Test Mode Select
Test Reset Signal
Test Clock
Test Data In
Test Data Out
Test Mode Select
Returned Test Clock
JTAG Selection
Debug Receive Data
Debug Transmit Data
Chip 2
Chip 1
ICE and JTAG
Debug Unit
Reset/Test
Tester
Input/Output
Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
Input
6221I–ATARM–17-Jul-09
Active Level
High
Low
Low