AT91SAM9260B-CU-999 Atmel, AT91SAM9260B-CU-999 Datasheet - Page 125

• Manufacturer Part Number: AT91SAM9260B-CU-999
• Description: IC MCU ARM9 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9260B-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.4
18.4.1
18.4.2
18.4.3
18.5
6221I–ATARM–17-Jul-09
Special Bus Granting Techniques
Arbitration
No Default Master
Last Access Master
Fixed Default Master
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access
requests from some masters. This mechanism reduces latency at first accesses of a burst or sin-
gle transfer. The bus granting mechanism sets a default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to
its associated default master. A slave can be associated with three kinds of default masters: no
default master, last access master and fixed default master.
At the end of the current access, if no other request is pending, the slave is disconnected from
all masters. No Default Master suits Low Power mode.
At the end of the current access, if no other request is pending, the slave remains connected to
the last master that performed an access request.
At the end of the current access, if no other request is pending, the slave connects to its fixed
default master. Unlike last access master, the fixed master doesn’t change unless the user mod-
ifies it by a software action (field FIXED_DEFMSTR of the related MATRIX_SCFG).
To change from one kind of default master to another, the Bus Matrix user interface provides the
Slave Configuration Registers, one for each slave, that set a default master for each slave. The
Slave Configuration Register contains two fields, DEFMSTR_TYPE and FIXED_DEFMSTR. The
2-bit DEFMSTR_TYPE field is used to select the default master type (no default, last access
master, fixed default master) whereas the 4-bit FIXED_DEFMSTR field is used to select a fixed
default master provided that DEFMSTR_TYPE is set to fixed default master. Refer to
18.6 ”Bus Matrix User Interface” on page
The Bus Matrix provides an arbitration mechanism that reduces latency when conflicting cases
occur, in particular when two or more masters try to access the same slave at the same time.
One arbiter per AHB slave is provided, thus arbitrating each slave differently.
The Bus Matrix provides the user the possibility to choose between 2 arbitration types for each
slave:
This choice is made through the field ARBT of the Slave Configuration Registers
(MATRIX_SCFG).
Each algorithm may be complemented by selecting a default master configuration for each
slave.
When a re-arbitration has to be done, it is realized only under specific conditions described in
Section 18.5.1 ”Arbitration Rules” on page
1. Round-Robin Arbitration (the default)
2. Fixed Priority Arbitration
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