AT91SAM9260B-CU-999 Atmel, AT91SAM9260B-CU-999 Datasheet - Page 748

• Manufacturer Part Number: AT91SAM9260B-CU-999
• Description: IC MCU ARM9 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9260B-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

40.10.2
Table 40-28. ISI Timings with Peripheral Supply 3.3V
Table 40-29. ISI Timings with Peripheral Supply 2.5V
Table 40-30. ISI Timings with Peripheral Supply 1.8V
40.10.3
748
Symbol
ISI1
ISI2
ISI3
Symbol
ISI1
ISI2
ISI3
Symbol
ISI1
ISI2
ISI3
AT91SAM9260
ISI
MCI
Parameter
DATA/VSYNC/HSYNC setup time
DATA/VSYNC/HSYNC hold time
PIXCLK frequency
Parameter
DATA/VSYNC/HSYNC setup time
DATA/VSYNC/HSYNC hold time
PIXCLK frequency
Parameter
DATA/VSYNC/HSYNC setup time
DATA/VSYNC/HSYNC hold time
PIXCLK frequency
Figure 40-11. ISI Timing Diagram
The PDC interface block controls all data routing between the external data bus, internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine
that monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters
for the MMC/SD module (inner system) and the application (user programming).
These timings are given for a 25 pF load, corresponding to 1 MMC/SD Card.
Figure 40-12. MCI Timing Diagram
DATA[7:0]
VSYNC
HSYNC
PIXCLK
CMD_DAT Output
CMD_DAT Input
Bus Clock
5a
Valid Data
Min
0
3.96
Min
0
4.14
Min
0
4.56
3a
1
4a
Valid Data
2
3b
6a
Valid Data
Valid Data
1
7
Max
74.8
Max
69.8
Max
64.4
2
3
Valid Data
Valid Data
Valid Data
6b
5b
4b
6221I–ATARM–17-Jul-09
Units
ns
ns
MHz
Units
ns
ns
MHz
Units
ns
ns
MHz