AT91SAM9260-CU ATMEL [ATMEL Corporation], AT91SAM9260-CU Datasheet
AT91SAM9260-CU
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AT91SAM9260-CU Summary of contents
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... Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected ® ® Thumb Processor ® ® Technology for Java Acceleration AT91 ARM Thumb ® Microcontrollers AT91SAM9260 Summary 6221IS–ATARM–12-Aug-08 ...
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... VDDBU, VDDCORE and VDDPLL – 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os) – 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter) – Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os) • Available in a 208-lead PQFP Green and a 217-ball LFBGA Green Package AT91SAM9260 2 ™ Compliant ® Infrared Modulation/Demodulation, Manchester Encoding/Decoding ...
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... The AT91SAM9260 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM memories and a wide range of peripherals. The AT91SAM9260 embeds an Ethernet MAC, one USB Device Port, and a USB Host control- ler. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface ...
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... Figure 2-1. AT91SAM9260 Block Diagram AT91SAM9260 4 Filter 6221IS–ATARM–12-Aug-08 ...
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... Input Output Shutdown, Wakeup Logic Output Input ICE and JTAG Input Input Input Output Input Input Output AT91SAM9260 Active Level Comments 1.65V to 1.95V or 3.0V to3.6V 3.0V to 3.6V 1.65V to 3.6V 1.65V to 1.95V 3.0V to 3.6V 1.65V to 1.95V 1.65V to 1.95V Accepts between 0V and VDDBU. Driven at 0V only. Do not tie over VDDBU ...
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... CFOE CompactFlash Output Enable CFWE CompactFlash Write Enable CFIOR CompactFlash IO Read CFIOW CompactFlash IO Write CFRNW CompactFlash Read Not Write CFCS0 - CFCS1 CompactFlash Chip Select Lines AT91SAM9260 6 Type Reset/Test I/O Input Input Debug Unit - DBGU Input Output Advanced Interrupt Controller - AIC Input Input ...
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... Output SDRAM Controller Output Output Output Output Output Output Output Multimedia Card Interface MCI Output I/O I/O I/O I/O I/O I/O Input Output Input Output Input Input Input Synchronous Serial Controller - SSC Output Input I/O I/O I/O I/O AT91SAM9260 Active Level Comments Low Low Low Low Low High Low Low Low 7 ...
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... Receive Data Valid ERX0-ERX3 Receive Data ERXER Receive Error ECRS Carrier Sense and Data Valid ECOL Collision Detect EMDC Management Data Clock EMDIO Management Data Input/Output EF100 Force 100Mbit/sec. AT91SAM9260 8 Type Timer/Counter - TCx Input I/O I/O Serial Peripheral Interface - SPIx_ I/O I/O I/O I/O Output Two-Wire Interface I/O ...
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... Image Sensor Data clock AD0-AD3 Analog Inputs ADVREF Analog Positive Reference ADTRG ADC Trigger 6221IS–ATARM–12-Aug-08 Active Type Image Sensor Interface Input Output Input Input Input Analog to Digital Converter Analog Analog Input AT91SAM9260 Level Comments Provided by PCK1. Digital pulled-up inputs at reset 9 ...
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... PQFP Green package (0.5mm pitch) • 217-ball LFBGA Green package (0.8 mm ball pitch) 4.1 208-pin PQFP Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9260 Mechanical Character- istics” of the product datasheet. Figure 4-1. AT91SAM9260 10 shows the orientation of the 208-pin PQFP package. ...
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... A9 140 A8 141 VDDIOM 142 GND 143 A7 144 A6 145 A5 146 A4 147 A3 148 A2 149 NWR2/NBS2/A1 150 NBS0/A0 151 SDA10 152 AT91SAM9260 Signal Name Pin Signal Name RAS 157 ADVREF D0 158 PC0 D1 159 PC1 D2 160 VDDANA D3 161 PB10 D4 162 PB11 D5 163 PB20 D6 164 ...
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... SHDN 101 50 HDMA 102 51 HDPA 103 52 VDDIOP0 104 4.3 217-ball LFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the section “AT91SAM9260 Mechanical Character- istics” of the product datasheet. Figure 4-2. AT91SAM9260 12 Signal Name Pin CFIOW/NBS3/NWR3 153 CFIOR/NBS1/NWR1 154 SDCS/NCS1 155 CAS 156 shows the orientation of the 217-ball LFBGA package. ...
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... H4 D11 P2 H8 GND P3 H9 GND P4 H10 GND P5 H14 VDDCORE P6 H15 TCK P7 H16 NTRST P8 H17 PB18 P9 J1 PC19 P10 AT91SAM9260 Signal Name Pin Signal Name TDO P17 PB5 PB19 R1 NC TDI R2 GNDANA PB16 R3 PC29 PC24 R4 VDDANA PC20 R5 PB12 D15 R6 PB23 PC21 R7 GND ...
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... GNDBU, GNDPLL and GNDANA. 5.2 Power Consumption The AT91SAM9260 consumes about 500 µA of static current on VDDCORE at 25°C. This static current rises the temperature increases to 85°C. On VDDBU, the current does not exceed 10 µA in worst case conditions. ...
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... NRST and NTRST pins can be left unconnected. The NRST and NTRST pins both integrate a permanent pull-up resistor to VDDIOP0. Its value can be found in the table “DC Characteristics” in the section “AT91SAM9260 Electrical Charac- teristics” in the product datasheet. The NRST signal is inserted in the Boundary Scan. ...
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... The SHDN pin is an output only, which is driven by the Shutdown Controller. The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU. 6.7 Slow Clock Selection The AT91SAM9260 slow clock can be generated either by an external 32,768 Hz crystal or the on-chip RC oscillator. Table 6-1 Table 6-1. ...
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... Non-volatile Boot Memory can be internal or external – Selection is made by BMS pin sampled at reset 6221IS–ATARM–12-Aug-08 each quarter of the page system flexibility 32-bit data interface (Words) or fixed default master internal boot, one for external boot, one after remap AT91SAM9260 17 ...
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... Allows Handling of Dynamic Exception Vectors 7.2.1 Matrix Masters The Bus Matrix of the AT91SAM9260 manages six Masters, which means that each master can perform an access concurrently with others, according the slave it accesses is available. Each Master has its own decoder that can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings ...
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... USART1 Receive Channel – USART0 Receive Channel – ADC Receive Channel – SPI1 Receive Channel – SPI0 Receive Channel – SSC Receive Channel 6221IS–ATARM–12-Aug-08 AT91SAM9260 Masters to Slaves Access Internal ROM X UHP User Interface X External Bus Interface X Internal Peripherals ...
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... Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins AT91SAM9260 20 6221IS–ATARM–12-Aug-08 ...
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... Memories Figure 8-1. AT91SAM9260 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 0x4000 0000 EBI Chip Select 3/ ...
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... When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: AT91SAM9260 22 Table 8-1, “Internal Memory Mapping,” on page 22 Figure 8-1 on page summarizes the Internal Memory Mapping for each Master, depending on the Remap ...
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... The AT91SAM9260 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface ...
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... Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable • Energy-saving capabilities – Self-refresh, power down and deep power down modes supported AT91SAM9260 24 6221IS–ATARM–12-Aug-08 ...
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... ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes 6221IS–ATARM–12-Aug-08 detected erroneous pages AT91SAM9260 25 ...
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... System Controller can be addressed from a single pointer by using the stan- dard ARM instruction set, as the Load/Store instruction has an indexing mode of ±4 Kbytes. Figure 9-1 on page 27 Figure 8-1 on page 21 peripherals. AT91SAM9260 26 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller 6221IS–ATARM–12-Aug-08 ...
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... Block Diagram Figure 9-1. AT91SAM9260 System Controller Block Diagram periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP RC OSC OSC_SEL SLOW XIN32 CLOCK OSC XOUT32 XIN MAIN OSC XOUT PLLRCA PLLA ...
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... Embeds 2 PLLs – PLLA outputs 80 to 240 MHz clock – PLLB outputs 70 to 130 MHz clock – Both integrate an input divider to increase output accuracy – PLLB embeds its own filter AT91SAM9260 28 reset, user reset or watchdog reset 6221IS–ATARM–12-Aug-08 ...
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... Backup Mode, Main Power Supplies off, VDDBU powered by a battery 6221IS–ATARM–12-Aug-08 Clock Generator Block Diagram OSC_SEL XIN32 XOUT32 XIN XOUT PLLRCA processor stopped waiting for an interrupt AT91SAM9260 Clock Generator On Chip RC OSC Slow Clock SLCK Slow Clock Oscillator Main Main Clock ...
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... Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) AT91SAM9260 30 AT91SAM9260 Power Management Controller Block Diagram Master Clock Controller SLCK Prescaler MAINCK PLLACK /1,/2,/4, ...
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... Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from 9.12 Chip Identification • Chip ID: 0x019803A2 • JTAG ID: 0x05B1303F • ARM926 TAP ID: 0x0792603F 6221IS–ATARM–12-Aug-08 enabled processor Generator the ARM Processor’s ICE Interface AT91SAM9260 ® USART 31 ...
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... AT91SAM9260 32 defines the Peripheral Identifiers of the AT91SAM9260. A peripheral identifier is AT91SAM9260 Peripheral Identifiers Peripheral Mnemonic AIC SYSC PIOA PIOB PIOC ADC US0 US1 US2 MCI UDP TWI SPI0 SPI1 SSC - - TC0 TC1 ...
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... IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 10.3 Peripheral Signal Multiplexing on I/O Lines The AT91SAM9260 features 3 PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions ...
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... PA26 TIOA0 ERX3 PA27 TIOA1 ERXCK PA28 TIOA2 ECRS PA29 SCK1 ECOL (1) PA30 SCK2 RXD4 (1) PA31 SCK0 TXD4 Note: 1. Not available in the 208-lead PQFP package. AT91SAM9260 34 Application Usage Comments Reset State Power Supply I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 ...
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... I/O TIOB5 I/O ISI_D0 I/O ISI_D1 I/O ISI_D2 I/O ISI_D3 I/O ISI_D4 I/O ISI_D5 I/O ISI_D6 I/O ISI_D7 I/O ISI_PCK I/O ISI_VSYNC I/O ISI_HSYNC I/O I/O AT91SAM9260 Application Usage Power Supply Function Comments VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 ...
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... PC23 D23 PC24 D24 PC25 D25 PC26 D26 PC27 D27 PC28 D28 PC29 D29 PC30 D30 PC31 D31 Note: 1. Not available in the 208-lead PQFP package. AT91SAM9260 36 Peripheral B Comments Reset State SCK3 AD0 I/O PCK0 AD1 I/O PCK1 AD2 I/O SPI1_NPCS3 AD3 I/O SPI1_NPCS2 A23 SPI1_NPCS1 ...
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... RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation 6221IS–ATARM–12-Aug-08 peripherals Sensors and data per chip select AT91SAM9260 37 ...
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... Remote Loopback, Local Loopback, Automatic Echo The USART contains features allowing management of the Modem Signals DTR, DSR, DCD and RI. In the AT91SAM9260, only the USART0 implements these signals, named DTR0, DSR0, DCD0 and RI0. The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1 and CTS1, RTS2 and CTS2, respectively) are implemented in these USARTs for other features ...
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... Interrupt generation to signal receive and transmit completion • 28-byte transmit and 28-byte receive FIFOs • Automatic pad and CRC generation on transmitted frames • Address checking logic to recognize four 48-bit addresses • Support promiscuous mode where all valid frames are copied to memory 6221IS–ATARM–12-Aug-08 AT91SAM9260 39 ...
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... Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Four analog inputs shared with digital signals AT91SAM9260 40 6221IS–ATARM–12-Aug-08 ...
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... AT91SAM9260 Mechanical Characteristics 11.1 Package Drawings Figure 11-1. 217-ball LFBGA Package Drawing Table 11-1. Soldering Informations Ball Land Soldering Mask Opening Table 11-2. Device and 217-ball LFBGA Package Maximum Weight 450 Table 11-3. 217-ball LFBGA Package Characteristics Moisture Sensitivity Level Table 11-4. Package Reference JEDEC Drawing Reference JESD97 Classification 6221IS– ...
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... Figure 11-2. 208-lead PQFP Package Drawing Table 11-5. Device and 208-lead PQFP Package Maximum Weight 5.5 Table 11-6. 208-lead PQFP Package Characteristics Moisture Sensitivity Level Table 11-7. Package Reference JEDEC Drawing Reference JESD97 Classification AT91SAM9260 MS-022 e3 6221IS–ATARM–12-Aug-08 ...
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... A maximum of three reflow passes is allowed per component. 6221IS–ATARM–12-Aug-08 gives the recommended soldering profile from J-STD-20. Soldering Profile It is recommended to apply a soldering temperature higher than 250°C AT91SAM9260 BGA217 Green PQFP208 Green Package Package 3°C/sec. max. 3°C/sec. max. ...
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... AT91SAM9260 Ordering Information Table 12-1. AT91SAM9260 Ordering Information Marketing Revision Level A Marketing Revision Level B Ordering Code AT91SAM9260-QU AT91SAM9260-CU AT91SAM9260 44 Ordering Code Package AT91SAM9260B-QU PQFP208 AT91SAM9260B-CU BGA217 Temperature Operating Package Type Range Green Industrial -40°C to 85°C Green 6221IS–ATARM–12-Aug-08 ...
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... Revision History Table 13-1. Revision History - current version appears first Revision Comments 6221IS Section 12. ”AT91SAM9260 Ordering Information” on page 44 Version B added. Table 3-1, “Signal Description List” comments. Table 10-3, “Multiplexing on PIO Controller B” Table 3-1, “Signal Description List” ”Power Considerations” 6221HS voltage restraints removed. ...
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... Power consumption figures updated with current values in Consumption” on page 14 6221BS Change to signal name for pin 47 in page 11 . 6221AS First issue. AT91SAM9260 46 “Features” Table 4-2, “Pinout for 217-ball LFBGA Package,” and corrected range for SCKx pins; label change on matrix block. ...
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