AT91SAM9260B-CU-999 Atmel, AT91SAM9260B-CU-999 Datasheet - Page 677
![IC MCU ARM9 217LFBGA](/photos/12/13/121366/217-lfbga_sml.jpg)
AT91SAM9260B-CU-999
Manufacturer Part Number
AT91SAM9260B-CU-999
Description
IC MCU ARM9 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9260B-CU-999.pdf
(798 pages)
Specifications of AT91SAM9260B-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
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38.4.1
Figure 38-3. HSYNC and VSYNC Synchronization
Figure 38-4. SAV and EAV Sequence Synchronization
6221I–ATARM–17-Jul-09
Data Timing
DATA[7..0]
ISII_PCK
ISI_HSYNC
ISI_VSYNC
DATA[7..0]
ISI_PCK
is one. To optimize the bandwidth, the codec path should be enabled only when a capture is
required.
In grayscale mode, the input data stream is stored in memory without any processing. The 12-bit
data, which represent the grayscale level for the pixel, is stored in memory one or two pixels per
word, depending on the GS_MODE bit in the ISI_CR2 register. The codec datapath is not avail-
able when grayscale image is selected.
A frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames.
The two data timings using horizontal and vertical synchronization and EAV/SAV sequence syn-
chronization are shown in
In the VSYNC/HSYNC synchronization, the valid data is captured with the active edge of the
pixel clock (ISI_PCK), after SFD lines of vertical blanking and SLD pixel clock periods delay pro-
grammed in the control register.
The ITU-RBT.656-4 defines the functional timing for an 8-bit wide interface.
There are two timing reference signals, one at the beginning of each video data block SAV
(0xFF000080) and one at the end of each video data block EAV(0xFF00009D). Only data sent
between EAV and SAV is captured. Horizontal blanking and vertical blanking are ignored. Use of
the SAV and EAV synchronization eliminates the ISI_VSYNC and ISI_HSYNC signals from the
interface, thereby reducing the pin count. In order to retrieve both frame and line synchronization
properly, at least one line of vertical blanking is mandatory.
FF
00
SAV
00
80
1 line
Y
Y
Cb
Cb
Y
Y
Figure 38-3
Cr
Cr
Y
Y
Active Video
Cb
Frame
Cb
Y
and
Cr
Y
Figure
Y
Cr
Y
Cb
Y
38-4.
Cr
Y
Y
Cr
Cb FF
00
EAV
AT91SAM9260
00
9D
677
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