AT91SAM9260B-CU-999 Atmel, AT91SAM9260B-CU-999 Datasheet - Page 739

• Manufacturer Part Number: AT91SAM9260B-CU-999
• Description: IC MCU ARM9 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9260B-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

40.8.1
6221I–ATARM–17-Jul-09
SDRAMC Signals
These timings are given for a 10 pF load on SDCK and 50 pF on the data bus.
Table 40-22. SDRAMC Clock Signal
Table 40-23. SDRAMC Signals
Symbol
1/(t
Symbol
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
CPSDCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
)
Parameter
SDRAM Controller Clock Frequency
Parameter
SDCKE High before SDCK Rising Edge
SDCKE Low after SDCK Rising Edge
SDCKE Low before SDCK Rising Edge
SDCKE High after SDCK Rising Edge
SDCS Low before SDCK Rising Edge
SDCS High after SDCK Rising Edge
RAS Low before SDCK Rising Edge
RAS High after SDCK Rising Edge
SDA10 Change before SDCK Rising Edge
SDA10 Change after SDCK Rising Edge
Address Change before SDCK Rising Edge
Address Change after SDCK Rising Edge
Bank Change before SDCK Rising Edge
Bank Change after SDCK Rising Edge
CAS Low before SDCK Rising Edge
CAS High after SDCK Rising Edge
DQM Change before SDCK Rising Edge
DQM Change after SDCK Rising Edge
D0-D15 in Setup before SDCK Rising Edge
D0-D15 in Hold after SDCK Rising Edge
D16-D31 in Setup before SDCK Rising Edge
D16-D31 in Hold after SDCK Rising Edge
SDWE Low before SDCK Rising Edge
SDWE High after SDCK Rising Edge
D0-D15 Out Valid before SDCK Rising Edge
1.8V Supply
See
Supply
MCK Maximum Clock
1.8V
5.7
4.9
6.2
5.4
5.4
5.8
5.5
5.7
4.9
4.9
5.3
5.4
5.9
5.4
5.6
4.7
0.9
0.6
0.8
0.7
6.1
5.6
5.2
Clock Waveform
Parameters,” on
6
5
Table 40-7, “Master
page 729
AT91SAM9260
Frequency
Min
Max
Supply
Supply
3.3V
.
4.7
5.9
5.2
6.4
6.4
4.8
6.5
4.8
5.9
4.3
6.4
4.9
6.4
4.7
5.8
0.2
1.1
1.2
5.1
6.6
4.2
3.3V
5
4
6
0
Units
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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