ATMEGA645A-AU Atmel, ATMEGA645A-AU Datasheet - Page 70
![IC MCU AVR 64K FLASH 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA645A-AU
Manufacturer Part Number
ATMEGA645A-AU
Description
IC MCU AVR 64K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA645A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Processor Series
ATmega
Core
AVR
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA645A-AUR
Manufacturer:
HONEYWELL
Quantity:
101
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13.2.2
13.2.3
13.2.4
70
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645
Toggling the Pin
Switching Between Input and Output
Reading the Pin Value
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 13-1 on page 70
Table 13-1.
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value
near the edge of the internal clock, but it also introduces a delay.
gram of the synchronization when reading an externally applied pin value. The maximum and
minimum propagation delays are denoted t
DDxn
0
0
0
1
1
PORTxn
0
1
1
0
1
Port Pin Configurations
(in MCUCR)
summarizes the control signals for the pin value.
PUD
X
0
1
X
X
Figure
Output
Output
Input
Input
Input
13-2, the PINxn Register bit and the preceding latch con-
I/O
pd,max
Pull-up
and t
Yes
No
No
No
No
pd,min
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
respectively.
Figure 13-3
shows a timing dia-
8285B–AVR–03/11
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