ATMEGA645A-AU Atmel, ATMEGA645A-AU Datasheet - Page 300
![IC MCU AVR 64K FLASH 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA645A-AU
Manufacturer Part Number
ATMEGA645A-AU
Description
IC MCU AVR 64K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA645A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Processor Series
ATmega
Core
AVR
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA645A-AUR
Manufacturer:
HONEYWELL
Quantity:
101
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4. The Flash is programmed one page at a time. The page size is found in
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
6. Any memory location can be verified by using the Read instruction which returns the con-
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
Table 26-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol
t
t
t
t
WD_FUSE
WD_FLASH
WD_EEPROM
WD_ERASE
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
page
address and data together with the Load Program Memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is
applied for a given address. The Program Memory Page is stored by loading the Write
Program Memory Page instruction with the 7 MSB of the address. If polling
not used, the user must wait at least t
26-15.) Accessing the serial programming interface before the Flash write operation
completes can result in incorrect programming.
data together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling
user must wait at least t
chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 2 LSB of the address and data together with the Load
EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading
the Write EEPROM Memory Page Instruction with the 4 MSB of the address. When using
EEPROM page access only byte locations loaded with the Load EEPROM Memory Page
instruction is altered. The remaining locations remain unchanged. If polling (
not used, the user must wait at least t
26-15). In a chip erased device, no 0xFF in the data file(s) need to be programmed.
tent at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
286. The memory page is loaded one byte at a time by supplying the 6 LSB of the
CC
power off
WD_EEPROM
before issuing the next byte (See
WD_EEPROM
WD_FLASH
before issuing the next page. (See
before issuing the next page (See
Minimum Wait Delay
(
RDY/BSY) is not used, the
4.5ms
4.5ms
3.6ms
9.0ms
Table
Table 26-7 on
26-15). In a
(
RDY/BSY) is
RDY/BSY
8285B–AVR–03/11
Table
Table
) is
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