ATMEGA645A-AU Atmel, ATMEGA645A-AU Datasheet - Page 199

• Manufacturer Part Number: ATMEGA645A-AU
• Description: IC MCU AVR 64K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA645A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Processor Series: ATmega
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3
20.3.1
8285B–AVR–03/11
Functional Descriptions
Three-wire Mode
ATmega165A/165PA/325A/325PA/3250A/3250PA/6
The 4-bit counter can be both read and written via the data bus, and can generate an overflow
interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock
source. This allows the counter to count the number of bits received or transmitted and generate
an interrupt when the transfer is complete. Note that when an external clock source is selected
the counter counts both clock edges. In this case the counter counts the number of edges, and
not the number of bits. The clock can be selected from three different sources: The USCK pin,
Timer/Counter0 Compare Match or from software.
The Two-wire clock control unit can generate an interrupt when a start condition is detected on
the Two-wire bus. It can also generate wait states by holding the clock pin low after a start con-
dition is detected, or after the counter overflows.
The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but
does not have the slave select (SS) pin functionality. However, this feature can be implemented
in software if necessary. Pin names used by this mode are: DI, DO, and USCK.
Figure 20-2. Three-wire Mode Operation, Simplified Diagram
Figure 20-2 on page 199
one as Slave. The two Shift Registers are interconnected in such way that after eight USCK
clocks, the data in each register are interchanged. The same clock also increments the USI’s 4-
bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to deter-
mine when a transfer is completed. The clock is generated by the Master device software by
toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR.
SLAVE
MASTER
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
shows two USI units operating in Three-wire mode, one as Master and
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
PORTxn
USCK
USCK
DO
DO
DI
DI
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