ATMEGA645A-AU Atmel, ATMEGA645A-AU Datasheet - Page 196

• Manufacturer Part Number: ATMEGA645A-AU
• Description: IC MCU AVR 64K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA645A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Processor Series: ATmega
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645
Receiver will generate a parity value for the incoming data and compare it to the UPM0n setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Table 19-9.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 19-10. USBSn Bit Settings
• Bit 2:1 – UCSZn[1:0]: Character Size
The UCSZn[1:0] bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 19-11. UCSZ Bits Settings
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCK).
Table 19-12. UCPOLn Bit Settings
UCPOLn
0
1
UCSZn2
UPMn1
0
0
0
0
1
1
1
1
0
0
1
1
Transmitted Data Changed
(Output of TxD Pin)
Rising XCK Edge
Falling XCK Edge
UPM Bits Settings
USBSn
0
1
UCSZn1
UPMn0
0
0
1
1
0
0
1
1
0
1
0
1
Stop Bit(s)
1-bit
2-bit
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
UCSZn0
0
1
0
1
0
1
0
1
Received Data Sampled (Input on RxD
Pin)
Falling XCK Edge
Rising XCK Edge
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
8285B–AVR–03/11