ATMEGA645A-AU Atmel, ATMEGA645A-AU Datasheet - Page 15

• Manufacturer Part Number: ATMEGA645A-AU
• Description: IC MCU AVR 64K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA645A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Processor Series: ATmega
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.6.1
6.7
8285B–AVR–03/11
Instruction Execution Timing
SPH and SPL – Stack Pointer
ATmega165A/165PA/325A/325PA/3250A/3250PA/6
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 6-4
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6-4.
Figure 6-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 6-5.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
shows the internal timing concept for the Register File. In a single clock cycle an ALU
shows the parallel instruction fetches and instruction executions enabled by the Har-
Result Write Back
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
R/W
R/W
SP7
15
–
7
0
0
clk
clk
CPU
CPU
SP6
R/W
R/W
14
–
6
0
0
SP5
R/W
R/W
CPU
13
–
5
0
0
T1
T1
, directly generated from the selected clock source for the
SP4
R/W
R/W
12
–
4
0
0
T2
SP3
R/W
R/W
T2
11
–
3
0
0
SP10
SP2
R/W
R/W
10
2
0
0
T3
T3
SP9
SP1
R/W
R/W
9
1
0
0
R/W
R/W
SP8
SP0
8
0
0
0
T4
T4
SPH
SPL
15