ATMEGA645A-AU Atmel, ATMEGA645A-AU Datasheet - Page 243

• Manufacturer Part Number: ATMEGA645A-AU
• Description: IC MCU AVR 64K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA645A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Processor Series: ATmega
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8285B–AVR–03/11
ATmega165A/165PA/325A/325PA/3250A/3250PA/6
When no alternate port function is present, the Input Data – ID – corresponds to the PINxn Reg-
ister value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output
Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – cor-
responds to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in
to make the scan chain read the actual pin value. For Analog function, there is a direct connec-
tion from the external pin to the analog circuit, and a scan chain is inserted on the interface
between the digital logic and the analog circuitry.
Figure 24-3. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.
Pullup Enable (PUE)
Output Control (OC)
Output Data (OD)
Input Data (ID)
0
1
From Last Cell
0
1
0
1
0
1
ShiftDR
ClockDR
D
D
D
FF2
FF1
FF0
To Next Cell
Q
Q
Q
UpdateDR
D
G
D
G
D
G
LD2
LD1
LD0
Q
Q
Q
0
1
0
1
0
1
EXTEST
Figure 24-4 on page 244
Vcc
243