AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 574

• Manufacturer Part Number: AT32UC3L064-AUT
• Description: MCU AVR32 64KB FLASH 48TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L064-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI/TWI/USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

• ETRGEDG: External Trigger Edge Selection
• LDBDIS: Counter Clock Disable with RB Loading
• LDBSTOP: Counter Clock Stopped with RB Loading
• BURST: Burst Signal Selection
• CLKI: Clock Invert
• TCCLKS: Clock Selection
32099F–11/2010
ETRGEDG
TCCLKS
BURST
0
1
2
3
0
1
2
3
4
5
6
7
0
1
2
3
0: TIOB is used as an external trigger.
1: Counter clock is disabled when RB loading occurs.
0: Counter clock is not disabled when RB loading occurs.
1: Counter clock is stopped when RB loading occurs.
0: Counter clock is not stopped when RB loading occurs.
1: The counter is incremented on falling edge of the clock.
0: The counter is incremented on rising edge of the clock.
Burst Signal Selection
The clock is not gated by an external signal
XC0 is ANDed with the selected clock
XC1 is ANDed with the selected clock
XC2 is ANDed with the selected clock
Clock Selected
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
Edge
none
rising edge
falling edge
each edge
AT32UC3L016/32/64
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