AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 450
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 450 of 858
- Download datasheet (13Mb)
• BITS: Bits Per Transfer
• CSAAT: Chip Select Active After Transfer
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
• NCPHA: Clock Phase
• CPOL: Clock Polarity
32099F–11/2010
DLYBCS
-------------------------------- -
The BITS field determines the number of data bits transferred. Reserved values should not be used.
1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested
on a different chip select.
0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and
if the two transfers occur on the same Chip Select.
1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of:
1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of
SPCK.
0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of
SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
1: The inactive state value of SPCK is logic level one.
0: The inactive state value of SPCK is logic level zero.
DLYBCS
---------------------- -
CLKSPI
CLKSPI
BITS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
+
(if DLYBCT field is different from 0)
1
(if DLYBCT field equals 0)
Bits Per Transfer
Reserved
Reserved
Reserved
10
11
12
13
14
15
16
8
9
4
5
6
7
AT32UC3L016/32/64
450
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