AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 279
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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Figure 15-2. Basic Mode WDT Timing Diagram, normal operation.
Figure 15-3. Basic Mode WDT Timing Diagram, no clear within T
15.5.1.6
15.5.2
32099F–11/2010
C L R .W D T C L R
W a tc h d o g re s e t
t= t
C L R .W D T C L R
W a tch d o g re se t
W rite o n e to
t= t
W rite o ne to
0
0
Window Mode
Watchdog Reset
If the WDT counter is not cleared within T
see
A watchdog reset will result in a reset and the code will start executing from the boot vector,
please refer to the Power Manager chapter for details. If the Disable After Reset (DAR) bit in the
CTRL Register is zero, the WDT counter will restart counting from zero when the watchdog reset
is released.
If the CTRL.DAR bit is one the WDT will be disabled after a watchdog reset. Only the CTRL.EN
bit will be changed after the watchdog reset. However, if WDTAUTO fuse is configured to enable
the WDT after a watchdog reset, and the CTRL.FCD bit is zero, writing a one to the CTRL.DAR
bit will have no effect.
The window mode can protect against tight loops of runaway code. This is obtained by adding a
ban period to timeout period. During the ban period clearing the WDT counter is not allowed.
If the WDT Mode (MODE) bit in the CTRL Register is one, the WDT is in window mode. Note
that the CTRL.MODE bit can only be changed when the WDT is disabled (CTRL.EN=0).
Figure 15-3 on page
T
T
p s e l
p se l
279.
psel
psel
.
a watchdog reset will be issued at the end of T
AT32UC3L016/32/64
T im e o u t
T im e o u t
279
psel
,
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