AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 437
![MCU AVR32 64KB FLASH 48TQFP](/photos/6/82/68248/313-48-vqfp_sml.jpg)
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 437 of 858
- Download datasheet (13Mb)
20.7.4
32099F–11/2010
SPI Slave Mode
register (MR.MODFDIS). In systems with open-drain I/O lines, a mode fault is detected when a
low level is driven by an external master on the NPCS0/NSS signal.
When a mode fault is detected, the Mode Fault Error bit in the SR (SR.MODF) is set until the SR
is read and the SPI is automatically disabled until re-enabled by writing a one to the SPI Enable
bit in the CR register (CR.SPIEN).
By default, the mode fault detection circuitry is enabled. The user can disable mode fault detec-
tion by writing a one to the Mode Fault Detection bit in the MR register (MR.MODFDIS).
When operating in slave mode, the SPI processes data bits on the clock provided on the SPI
clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master.
When NSS falls, the clock is validated on the serializer, which processes the number of bits
defined by the Bits Per Transfer field of the Chip Select Register 0 (CSR0.BITS). These bits are
processed following a phase and a polarity defined respectively by the CSR0.NCPHA and
CSR0.CPOL bits. Note that the BITS, CPOL, and NCPHA bits of the other Chip Select Registers
have no effect when the SPI is configured in Slave Mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
When all the bits are processed, the received data is transferred in the Receive Data Register
and the SR.RDRF bit rises. If the RDR register has not been read before new data is received,
the SR.OVRES bit is set. Data is loaded in RDR even if this flag is set. The user has to read the
SR register to clear the SR.OVRES bit.
When a transfer starts, the data shifted out is the data present in the Shift Register. If no data
has been written in the TDR register, the last data received is transferred. If no data has been
received since the last reset, all bits are transmitted low, as the Shift Register resets to zero.
When a first data is written in TDR, it is transferred immediately in the Shift Register and the
SR.TDRE bit rises. If new data is written, it remains in TDR until a transfer occurs, i.e. NSS falls
and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in
TDR is transferred in the Shift Register and the SR.TDRE bit rises. This enables frequent
updates of critical variables with single transfers.
Then, a new data is loaded in the Shift Register from the TDR. In case no character is ready to
be transmitted, i.e. no character has been written in TDR since the last load from TDR to the
Shift Register, the Shift Register is not modified and the last received character is retransmitted.
In this case the Underrun Error Status bit is set in SR (SR.UNDES).
Figure 20-9 on page 438
shows a block diagram of the SPI when operating in slave mode.
AT32UC3L016/32/64
437
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